Patents by Inventor Hyeon Soo Kim
Hyeon Soo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8674425Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.Type: GrantFiled: May 16, 2011Date of Patent: March 18, 2014Assignee: SK hynix Inc.Inventors: Sung Min Hwang, Hyeon Soo Kim
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Patent number: 8472875Abstract: The present invention relates to technology which performs wireless communications of a vehicle by selectively operating a wireless communications module of a vehicle connected to an AP (Access Point) which collects vehicle information according to the state of the vehicle. The present invention includes a vehicle information storage unit that stores vehicle information collected from each electronic control unit of a vehicle; a wireless communications module that performs wireless communications with an AP (Access Point); and a wireless communications controller that controls a connection state of the AP with the wireless communications module by selectively operating the wireless communications module according to the state of the vehicle, and sends the vehicle information to the AP through the wireless communications module.Type: GrantFiled: July 28, 2009Date of Patent: June 25, 2013Assignees: Hyundai Motor Company, Kia Motors CorporationInventors: Sang Woo Ji, Hyeon Soo Kim, Jae Hun Jeong
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Publication number: 20130084696Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.Type: ApplicationFiled: August 14, 2012Publication date: April 4, 2013Applicant: SK Hynix Inc.Inventors: Suk Ki KIM, Hyeon Soo KIM
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Publication number: 20120199938Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.Type: ApplicationFiled: May 16, 2011Publication date: August 9, 2012Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Sung Min Hwang, Hyeon Soo Kim
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Publication number: 20110159681Abstract: A method of manufacturing a nonvolatile memory device includes forming a tunnel insulating layer over a semiconductor substrate, forming tunnel insulating patterns to expose portions of the semiconductor substrate by removing portions of the tunnel insulating layer formed over isolation regions of the semiconductor substrate, forming a first conductive layer of single crystalline material over the tunnel insulating patterns and exposed portions of the semiconductor substrate, and forming a second conductive layer over the first conductive layer.Type: ApplicationFiled: December 20, 2010Publication date: June 30, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Sung Min Hwang, Hyeon Soo Kim
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Publication number: 20100075608Abstract: The present invention relates to technology which performs wireless communications of a vehicle by selectively operating a wireless communications module of a vehicle connected to an AP (Access Point) which collects vehicle information according to the state of the vehicle. The present invention includes a vehicle information storage unit that stores vehicle information collected from each electronic control unit of a vehicle; a wireless communications module that performs wireless communications with an AP (Access Point); and a wireless communications controller that controls a connection state of the AP with the wireless communications module by selectively operating the wireless communications module according to the state of the vehicle, and sends the vehicle information to the AP through the wireless communications module.Type: ApplicationFiled: July 28, 2009Publication date: March 25, 2010Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATIONInventors: Sang Woo Ji, Hyeon Soo Kim, Jae Hun Jeong
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Publication number: 20090312250Abstract: The present inventors show that a brief exposure to EGF stimulates insulin secretion glucose-independently via a Ca2+ influx- and PLD2-dependent mechanism. Furthermore, the present invention shows that EGF is a novel secretagogue that lowers plasma glucose levels in normal and diabetic mice, suggesting the potential for EGF treatment in diabetes.Type: ApplicationFiled: July 16, 2007Publication date: December 17, 2009Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATIONInventors: Sung-Ho Ryu, Hye-Young Lee, Kyung-Moo Yea, Byoung-Dae Lee, Young-Chan Chae, Hyeon-Soo Kim, Seon-Hee Kim, Pann-Ghill Suh
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Patent number: 7335554Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming a sacrificial layer over the substrate and filling the first trench, etching the sacrificial layer to have a portion of the sacrificial layer remain in the first trench in the BLC region of the substrate, forming a second trench extending horizontally by etching the substrate underneath the first trench, and filling the first and second trenches to form an isolation structure.Type: GrantFiled: December 29, 2006Date of Patent: February 26, 2008Assignee: Hynix Semiconductor Inc.Inventors: Jong-Man Kim, Hyeon-Soo Kim
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Publication number: 20070254427Abstract: A method for fabricating a semiconductor device includes forming a first trench by etching a substrate already provided with a storage node contact (SNC) region and a bit line contact (BLC) region, forming a protection layer on sidewalls of the first trench, forming a sacrificial layer over the substrate and filling the first trench, etching the sacrificial layer to have a portion of the sacrificial layer remain in the first trench in the BLC region of the substrate, forming a second trench extending horizontally by etching the substrate underneath the first trench, and filling the first and second trenches to form an isolation structure.Type: ApplicationFiled: December 29, 2006Publication date: November 1, 2007Applicant: Hynix Semiconductor Inc.Inventors: Jong-Man Kim, Hyeon-Soo Kim
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Patent number: 7148129Abstract: A method of growing a semiconductor layer in a selective area by Metal Organic Chemical Vapor Deposition (MOCVD) and a mask pattern for s ame, includes a first mask pattern and a second mask pattern that are formed on a semiconductor substrate having a (100) crystalline plane. The first mask pattern has a first window wider than the selective area and a second mask pattern has a second window and a third window. The second window is defined by spacing the second mask pattern from the first mask pattern, in correspondence with a blocking area for blocking the surface migration of III-group semiconductor source gases at edges of the first window. The third window is as wide as the selective area. The semiconductor layer is grown by MOCVD on the semiconductor substrate exposed by the second and third windows. Trenches can be etched in the second and third windows and growth layers extend from the trench beyond the surface of the InP to block gas dispersion.Type: GrantFiled: March 22, 2004Date of Patent: December 12, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Churl Bang, Eun-Hwa Lee, Hyeon-Soo Kim, Jung-Kee Lee, Jun-Youn Kim
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Publication number: 20050157766Abstract: A semiconductor optical device including an SSC region includes a semiconductor substrate, a lower clad layer grown on the semiconductor substrate, and an upper clad layer grown on the lower clad layer. The semiconductor optical device with an SSC (Spot Size Conversion) area includes a gain area including an active layer grown between the lower clad layer and the upper clad layer to generate/amplify an optical signal; and an SSC (Spot Size Conversion) area including a waveguide layer extended from the active layer positioned between the lower and upper clad layers, such that it performs a spot size conversion (SSC) process of the optical signal generated from the gain area and generates the SSC-processed optical signal.Type: ApplicationFiled: June 9, 2004Publication date: July 21, 2005Inventors: Hyeon-Soo Kim, Young-Churl Bang, Jung-Kee Lee, Eun-Hwa Lee, Jun-Youn Kim
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Publication number: 20050103259Abstract: A method of growing a semiconductor layer in a selective area by Metal Organic Chemical Vapor Deposition (MOCVD) and a mask pattern for s ame, includes a first mask pattern and a second mask pattern that are formed on a semiconductor substrate having a (100) crystalline plane. The first mask pattern has a first window wider than the selective area and a second mask pattern has a second window and a third window. The second window is defined by spacing the second mask pattern from the first mask pattern, in correspondence with a blocking area for blocking the surface migration of III-group semiconductor source gases at edges of the first window. The third window is as wide as the selective area. The semiconductor layer is grown by MOCVD on the semiconductor substrate exposed by the second and third windows. Trenches can be etched in the second and third windows and growth layers extend from the trench beyond the surface of the InP to block gas dispersion.Type: ApplicationFiled: March 22, 2004Publication date: May 19, 2005Inventors: Young-Churl Bang, Eun-Hwa Lee, Hyeon-Soo Kim, Jung-Kee Lee, Jun-Youn Kim
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Patent number: 6551913Abstract: The present invention relates to a semiconductor technology and more specifically to a method of fabricating a gate electrode of a semiconductor device, where a re-oxidation process that may cause an abnormal oxidation can be eliminated. In a polysilicon/silicide structure or polysilicon/metal structure of gate electrode, a step of etching side parts of gate electrode is performed without any etch mask after gate patterning. Here, the etch can be made by wet or dry etch using an etchant having high selectivity of polysilicon film to a gate oxide film, so that the damaged gate oxide part during the gate patterning is allowed not to make a role of the gate insulating film itself, thereby eliminating the re-oxidation process.Type: GrantFiled: June 30, 1999Date of Patent: April 22, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyeon Soo Kim, Chang Seo Park
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Patent number: 6503806Abstract: Disclosed is a method for forming a gate electrode of a semiconductor device, the method comprises the steps of: stacking a gate oxide film, a doped first silicon film, a diffusion preventing film, a metal film having a high melting point and a mask insulating film on a semiconductor substrate; forming a gate electrode by patterning a resultant stack structure; forming a second silicon film on an entire surface of a resultant structure; forming an oxidation preventing film on an entire surface of a resultant structure; forming a spacer on a side wall of the gate electrode by anisotrophically etching the oxidation preventing film and the second silicon film; and forming a gate reoxide film on the semiconductor substrate by oxidizing the semiconductor substrate.Type: GrantFiled: December 27, 1999Date of Patent: January 7, 2003Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Hyeon Soo Kim
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Patent number: 6376874Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.Type: GrantFiled: June 1, 2000Date of Patent: April 23, 2002Assignee: Samsung Electronics Co., Ltd.Inventor: Hyeon-Soo Kim
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Publication number: 20020001935Abstract: A method of forming a gate electrode in semiconductor device which can prevent transformation of the gate electrode, is disclosed. According to the present invention, a gate insulating layer, a doped polysilicon layer and a sacrificial layer are formed on a semiconductor substrate, sequentially. The sacrificial layer and the polysilicon layer are then etched in the shape of a gate electrode to form a sacrificial pattern and a polysilicon pattern. Next, the substrate is re-oxidized to form a re-oxidation layer on the side walls of the polysilicon pattern and LDD ions are implanted into the substrate of both sides of the re-oxidation layer. A spacer of an insulating layer is then formed on the side walls of the sacrificial pattern and the re-oxidation layer and impurity ions of a high concentration are implanted into the substrate of both sides of the spacer. Thereafter, an intermediate insulating layer is formed on the overall substrate and etched to expose the surface of the sacrificial pattern.Type: ApplicationFiled: November 5, 1999Publication date: January 3, 2002Inventors: HYEON SOO KIM, JIN HONG LEE, IN SEOK YEO
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Patent number: 6333241Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.Type: GrantFiled: June 24, 1999Date of Patent: December 25, 2001Assignee: Samsung Electronics Co., Ltd.Inventor: Hyeon-Soo Kim
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Patent number: 6333250Abstract: A method of forming a gate electrode in a semiconductor device is disclosed. A method of forming a gate electrode in a semiconductor device according to the present invention includes steps of: forming a gate oxide layer, a polysilicon layer, a diffusion barrier layer, a metal layer and a mask layer on a semiconductor substrate, in sequence; patterning the mask layer, the metal layer and the diffusion barrier layer to the first width; patterning the mask layer, the metal layer and the diffusion barrier layer having the first width to a second width by wet etching; forming a spacer on the side walls of the mask layer, the metal layer and the diffusion barrier layer having the second width; and patterning the polysilicon layer and the gate oxide layer using the mask layer and the spacer as an etch barrier.Type: GrantFiled: December 14, 1999Date of Patent: December 25, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Hyeon Soo Kim
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Patent number: 6277738Abstract: The present invention relates to a method of manufacturing a semiconductor device, which is capable of effectively removing a WO3 film generated on a tungsten silicide during contact hole etch that opens a gate electrode including the tungsten silicide as its top film by selectively etching a interlayer insulating film. The WO3 film is removed by a washing process using an alkaline solution such as TMAH(tetra-methyl-ammonium-hydroxide) or NH4OH solution. The effective removal of the WO3 film reduces the contact resistance between a conductive material layer to be formed in the contact hole by a later process and the gate electrode, thereby improving the operative characteristics of the semiconductor device. TMAH solution used in the washing process has a high selectivity of WO3 film relative to a thermal oxide film or a BPSG film that is generally used as the interlayer insulating film.Type: GrantFiled: July 18, 2000Date of Patent: August 21, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyung Bok Choi, Chang Seo Park, Hyeon Soo Kim
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Patent number: 6197693Abstract: Generally, after etching process for gate electrode patterning, oxidation process is performed to compensate for etching damage. There is provided a method for forming a gate electrode of a semiconductor device, which prevents the metal layer comprised of the gate electrode for being oxidized in such an oxidation process. In the present invention, a polysilicon layer is etched to form a gate electrode pattern and re-oxidation process is performed to compensate for the etching damage. After this, an inter-layer insulating layer is formed over the entire structure and partially removed so as to expose the polysilicon layer. A part of the polysilicon layer is then selectively removed to form an opening in the inter-layer insulating layer. Here, the other part of the polysilicon layer, which will be connected to a metal layer later, is exposed through the opening. The metal layer is then buried within the opening to complete the formation of the gate electrode made of poly-metal structure.Type: GrantFiled: June 9, 1999Date of Patent: March 6, 2001Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Hyeon Soo Kim, Sang Do Lee