Abstract: Proposed are a complex catalyst containing an imine-based ligand for polymerizing a cyclic olefin-based monomer and a method of preparing a cyclic olefin-based polymer using the same. More particularly, proposed are a complex catalyst containing an imine-based ligand for polymerizing a cyclic olefin-based monomer, which can provide the complex catalyst containing the imine-base ligand having high activity in polymerizing the cyclic olefin-based monomer and can prepare a cyclic olefin-based polymer with high activity by polymerizing the cyclic olefin-based monomer in the presence of the complex catalyst containing the imine-based ligand, and a method of preparing a cyclic olefin-based polymer using the same.

Abstract: An electronic device including an antenna is provided. The electronic device includes a housing and a sliding plate, wherein the housing comprises an antenna circuit unit arranged on a side surface corresponding to the sliding operation direction of the sliding plate, and a contact unit for electrically connecting the housing and the sliding plate, wherein the antenna circuit unit further includes, as a radiator, at least one frame arranged on the side surface, wherein the housing and the plate form a space, and wherein the space, the contact unit, and the antenna circuit unit can form a cavity antenna.

Abstract: According to various embodiments, an electronic device includes: a first housing including a first area, a second housing coupled to be slidable in a first direction from the first housing and including a second area overlapping the first area in a slide-in state, an antenna structure disposed in the first housing to overlap the first area when the first housing is viewed from the top, a conductive part disposed in the second area and electromagnetically connected to the antenna structure in the slide-in state, and wireless communication circuitry electrically connected to the antenna structure. The wireless communication circuitry may be configured to transmit and/or receive radio signals in at least one designated frequency band through the antenna structure and the conductive part in the slide-in state.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data of an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data of an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A processor-implemented neural network method includes: obtaining, from a memory, data an input feature map and kernels having a binary-weight, wherein the kernels are to be processed in a layer of a neural network; decomposing each of the kernels into a first type sub-kernel reconstructed with weights of a same sign, and a second type sub-kernel for correcting a difference between a respective kernel, among the kernels, and the first type sub-kernel; performing a convolution operation by using the input feature map and the first type sub-kernels and the second type sub-kernels decomposed from each of the kernels; and obtaining an output feature map by combining results of the convolution operation.

Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.

Abstract: A semiconductor device includes a first gate electrode provided in a jumper region of a substrate and extending in a first direction, first source/drain regions provided at both sides of the first gate electrode, and a connecting contact electrically connecting the first gate electrode and the first source/drain regions to each other. The connecting contact includes first sub-contacts disposed at both sides of the first gate electrode and connected to the first source/drain regions, and a second sub-contact extending in a second direction intersecting the first direction. The second sub-contact is connected to the first sub-contacts and is in contact with a top surface of the first gate electrode. In the first direction, each of the first sub-contacts has a first width and the second sub-contact has a second width smaller than the first width.