Abstract: Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains ac

Abstract: Provided is a Java bytecode translating method which includes: a bytecode fetch step (S1 10) that fetches a Java bytecode from a Java class file; a static field address detection and data processing step (S140) which gains access to a field (130) according to a first field address (FA1) and processes data; a static field address storage step (S 150) that stores a first upper field address (FAU1) including upper bits among bits of the first field address (FA1) in a first storage portion (110), and which stores a first lower field address (FAD1) including remainder lower bits excluding the first upper field address (FAU1) among the bits of the first field address (FA1) in an operand field (120b); a static operation code translating step (S 160) that translates an operation code stored in an operation code field (120a) into a new static field accessing operation code (NOPA); a first field address creation step (S240) that creates a second field address (FA2); and a first data processing step (S250) that gains ac

Abstract: An apparatus includes an instruction word storage for storing a plurality of general instruction words and extended instruction words, a temporary storage unit including a plurality of buffers for pre-fetching and storing the plurality of instruction words from the instruction word storage, an instruction word search unit for receiving and decoding the plurality of instruction words pre-fetched and outputting a position signal of a general instruction word and the positions of one or more successive extended instruction words stored in the temporary storage a selector for selecting a buffer in which a general instruction word is stored and outputting the general instruction word sequentially, according to the position signal a general instruction word parser for receiving a general instruction word from the selector and outputting a plurality of control signals for executing the general instruction word simultaneously, an extended data parser is provided for performing an operational processing of operands of

Abstract: The present invention provides a method of implementing random number generators, which makes efficient hardware implementations possible, in a way of converting the multiplication and addition operations and the modulo operations into a series of addition operations.