Patents by Inventor Hyeong-geun An

Hyeong-geun An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7023037
    Abstract: A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: April 4, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hag-ju Cho, Hyeong-geun An
  • Patent number: 6815227
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Geun An
  • Patent number: 6815226
    Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
    Type: Grant
    Filed: July 7, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Kyu-Mann Lee, Yong-Tak Lee, Hyeong-Geun An
  • Publication number: 20040183116
    Abstract: A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g.,. an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
    Type: Application
    Filed: March 30, 2004
    Publication date: September 23, 2004
    Inventors: Hag-ju Cho, Hyeong-geun An
  • Publication number: 20040137648
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Geun An
  • Publication number: 20040135182
    Abstract: Ferroelectric capacitors include a support insulating film on an integrated circuit substrate and having a trench therein. A lower electrode is on sidewalls and a bottom surface of the trench. A seed conductive film covers the lower electrode. A ferroelectric film is provided on the support insulating film and the seed conductive film and an upper electrode is provided on the ferroelectric film. The lower electrode may fill the trench and the ferroelectric film may extend over all of the seed conductive film and the support insulating film adjacent the seed conductive film.
    Type: Application
    Filed: November 10, 2003
    Publication date: July 15, 2004
    Inventors: Hyeong-Geun An, Sang-Woo Lee, Hyoung-Joon Kim
  • Patent number: 6740531
    Abstract: A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: May 25, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hag-ju Cho, Hyeong-geun An
  • Patent number: 6717197
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: April 6, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Geun An
  • Patent number: 6686620
    Abstract: A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: February 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Soon-Oh Park
  • Publication number: 20040005724
    Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
    Type: Application
    Filed: July 7, 2003
    Publication date: January 8, 2004
    Applicant: Samsung Electronics
    Inventors: Kyu-Mann Lee, Yong-Tak Lee, Hyeong-Geun An
  • Patent number: 6664578
    Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern is performed.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: December 16, 2003
    Assignee: Samsung Electronics
    Inventors: Kyu-Mann Lee, Yong-Tak Lee, Hyeong-Geun An
  • Publication number: 20030057462
    Abstract: A ferroelectric memory device and a method of fabricating the same are provided. The ferroelectric memory device includes at least two capacitor patterns and a plate line. Each of the capacitor patterns includes a lower electrode, a ferroelectric layer, and an upper electrode that are stacked on a semiconductor substrate. A top of the plate line is covered with an oxygen barrier layer, and a sidewall of the plate line is covered with an oxygen barrier spacer.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 27, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Geun An
  • Publication number: 20030035313
    Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern in performed.
    Type: Application
    Filed: April 30, 2002
    Publication date: February 20, 2003
    Inventors: Kyu-Mann Lee, Yong-Tak Lee, Hyeong-Geun An
  • Publication number: 20020153550
    Abstract: A FRAM having a ferroelectric capacitor comprises a cylindrical type bottom electrode. A ferroelectric film is thinly stacked over the bottom electrode, and the first portion of the top electrode formed over and conformal to the ferroelectric film. A void that is left between sidewalls of the first portion of the electrode over the ferroelectric film is then filled with fill material for a fill layer. The fill material of the fill layer is then planarized to be level with and expose an upper surface of the first portion of the top electrode. A second portion of the top electrode is then formed over the fill layer and in contact with the exposed, e.g. peripheral regions of the first portion of the electrode. The fill material of the fill layer may be formed of polysilicon, silicon oxide or other material such as another metal.
    Type: Application
    Filed: March 27, 2002
    Publication date: October 24, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Geun An, Soon-Oh Park
  • Publication number: 20020021544
    Abstract: A dielectric region, such as a ferroelectric dielectric region of an integrated circuit capacitor, is protected by a multi-layer insulation structure including a first relatively thin insulation layer, e.g., an aluminum oxide or other metal oxide layer, and a second, thicker insulating layer, e.g., a second aluminum oxide or other metal oxide layer. Before formation of the second insulation layer, the first insulation layer and the dielectric preferably annealed, which can increase a remnant polarization of the dielectric region. The first insulation layer can serve as a hydrogen diffusion barrier during formation of the second insulation layer and other overlying structures. In this manner, degradation of the dielectric can be reduced. Devices and fabrication methods are discussed.
    Type: Application
    Filed: August 7, 2001
    Publication date: February 21, 2002
    Inventors: Hag-ju Cho, Hyeong-geun An