Abstract: Provided is a micro electro mechanical system (MEMS) resonating accelerometer. The MEMS resonating accelerometer according to the present invention comprises: a first inertial mass; a second inertial mass which is spaced at a predetermined distance from the first inertial mass on a first axis; an elastic body which is provided between the first and second inertial masses so as to apply elasticity; and a tuning fork which is connected to the elastic body and measures the change of frequency according to acceleration, wherein the longitudinal direction of the tuning fork is parallel to a second axis which is perpendicular to the first axis, the elastic body has an opening portion being in a circular shape with a portion thereof removed, and one end of the tuning fork penetrates the opening portion and is connected to the inner surface of the elastic body.

Abstract: Provided is a micro electro mechanical system (MEMS) resonating accelerometer. The MEMS resonating accelerometer according to the present invention comprises: a first inertial mass; a second inertial mass which is spaced at a predetermined distance from the first inertial mass on a first axis; an elastic body which is provided between the first and second inertial masses so as to apply elasticity; and a tuning fork which is connected to the elastic body and measures the change of frequency according to acceleration, wherein the longitudinal direction of the tuning fork is parallel to a second axis which is perpendicular to the first axis, the elastic body has an opening portion being in a circular shape with a portion thereof removed, and one end of the tuning fork penetrates the opening portion and is connected to the inner surface of the elastic body.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments relate to a method for manufacturing a semiconductor device including forming a well having two ends in a semiconductor substrate. A shallow trench isolation (STI) is formed by etching both ends of the well and the semiconductor substrate adjacent both ends of the well. A gate oxide film and a photoresist film are formed over the upper surface of the semiconductor substrate including the STI. The photoresist film is patterned for an impurity ion implant into one side area including the edge of the side wall of the STI. A barrier area is formed by implanting an impurity ion into one side area including the side wall edge of the STI using the patterned photoresist film as a mask.

Abstract: Embodiments relate to a semiconductor device. According to embodiments, a semiconductor device may include a plurality of wells formed on a substrate, threshold voltage control ion layers formed around surfaces of the wells, device isolation layers arranged between the wells, ion compensation layers formed on edges and bottoms of the device isolation layers, and a gate formed on the well.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the device, which suppresses off-current by improving the problem of leakage current due to hump characteristics, making it possible to maximize the reliability of the device. Embodiments relate to a method for manufacturing a semiconductor device including forming a well having two ends in a semiconductor substrate. A shallow trench isolation (STI) is formed by etching both ends of the well and the semiconductor substrate adjacent both ends of the well. A gate oxide film and a photoresist film are formed over the upper surface of the semiconductor substrate including the STI. The photoresist film is patterned for an impurity ion implant into one side area including the edge of the side wall of the STI. A barrier area is formed by implanting an impurity ion into one side area including the side wall edge of the STI using the patterned photoresist film as a mask.

Abstract: Embodiments relate to a semiconductor device. According to embodiments, a semiconductor device may include a plurality of wells formed on a substrate, threshold voltage control ion layers formed around surfaces of the wells, device isolation layers arranged between the wells, ion compensation layers formed on edges and bottoms of the device isolation layers, and a gate formed on the well.