Abstract: An electrically page erasable and programmable read only memory device is an EEPROM device which is erasable page by page, and consists of flash-type floating gate transistors as the memory cells. The memory cell array of the device is divided by a plurality of pages, wherein each page comprises a plurality of bit lines, a plurality of common source lines, and a plurality of word lines. A plurality of erase selection circuits are arranged and correspond to the respective pages in order to erase the cells in a selected page, wherein each erase selection circuit comprises a passing transistor, a gate, a voltage stabilizing transistor, and an erasing line.