Patents by Inventor Hyeong-Mo Yang
Hyeong-Mo Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9595582Abstract: A metal-oxide-semiconductor field-effect transistor device includes a first active area, a first gate electrode configured to cross the first active area and extend in a Y direction, and define a first source area and a first drain area, first gate contacts disposed on the first gate electrode to align on a first virtual gate passing line extending in the Y direction, first source contacts disposed on the first source area to align on a first virtual source passing line extending in the Y direction, and first drain contacts disposed on the first drain area to align on a first virtual drain passing line extending in the Y direction, wherein at least one of the first drain contacts is disposed to align on any one of first virtual X-straight lines configured to pass between the first source contacts and extend parallel in an X direction perpendicular to the Y direction.Type: GrantFiled: February 25, 2015Date of Patent: March 14, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hoon Lee, Nok-Hyun Ju, Hyeong-Mo Yang, Sung-Ii Chang, Chan-Ho Lee
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Publication number: 20150372085Abstract: A metal-oxide-semiconductor field-effect transistor device includes a first active area, a first gate electrode configured to cross the first active area and extend in a Y direction, and define a first source area and a first drain area, first gate contacts disposed on the first gate electrode to align on a first virtual gate passing line extending in the Y direction, first source contacts disposed on the first source area to align on a first virtual source passing line extending in the Y direction, and first drain contacts disposed on the first drain area to align on a first virtual drain passing line extending in the Y direction, wherein at least one of the first drain contacts is disposed to align on any one of first virtual X-straight lines configured to pass between the first source contacts and extend parallel in an X direction perpendicular to the Y direction.Type: ApplicationFiled: February 25, 2015Publication date: December 24, 2015Inventors: Jae-Hoon Lee, Nok-Hyun Ju, Hyeong-Mo Yang, Sung-II Chang, Chan-Ho Lee
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Patent number: 7091094Abstract: The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different according to the parts. The semiconductor device according to the present invention includes a semiconductor substrate including active regions where a semiconductor device is to be fabricated and isolation regions for electrically isolating the active regions. A gate electrode is formed to go across the active region. A source and a drain are formed in the active region at both sides of the gate electrode, wherein the length of the gate electrode on the upper surface of the sides of the active region is longer than the length of the gate electrode of the center of the active region.Type: GrantFiled: August 30, 2002Date of Patent: August 15, 2006Assignee: Hynix Semiconductor Inc.Inventors: Jeong-Hwan Son, Hyeong-Mo Yang
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Publication number: 20060088964Abstract: A method of forming an SRAM cell, having two transfer transistors, two driver transistors, and two load devices which are connected with one another in the form of a flip-flop is provided. In particular, after defining an active region and an inactive region on a silicon substrate, a gate electrode conductive pattern of the transistors is formed on the silicon substrate having the active region and the inactive region formed therein along a channel width direction (X-axis direction). Then, after forming a pocket ion implantation region under the conductive pattern, by performing a photolithography process on the conductive pattern along a channel length direction (Y-axis direction), the gate electrodes of the transistors are formed. Even though the gate electrodes are misaligned, impurities for pocket ion implantation are not injected into the gate extension along the channel width direction.Type: ApplicationFiled: June 8, 2005Publication date: April 27, 2006Inventors: Hyuck-chai Jung, Hyeong-mo Yang
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Publication number: 20020195671Abstract: The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different according to the parts. The semiconductor device according to the present invention includes a semiconductor substrate including active regions where a semiconductor device is to be fabricated and isolation regions for electrically isolating the active regions. A gate electrode is formed to go across the active region. A source and a drain are formed in the active region at both sides of the gate electrode, wherein the length of the gate electrode on the upper surface of the sides of the active region is longer than the length of the gate electrode of the center of the active region.Type: ApplicationFiled: August 30, 2002Publication date: December 26, 2002Applicant: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong-Hwan Son, Hyeong-Mo Yang
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Patent number: 6462389Abstract: The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different according to the parts. The semiconductor device according to the present invention includes a semiconductor substrate including active regions where a semiconductor device is to be fabricated and isolation regions for electrically isolating the active regions. A gate electrode is formed to go across the active region. A source and a drain are formed in the active region at both sides of the gate electrode, wherein the length of the gate electrode on the upper surface of the sides of the active region is longer than the length of the gate electrode of the center of the active region.Type: GrantFiled: January 23, 2001Date of Patent: October 8, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong-Hwan Son, Hyeong-Mo Yang
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Patent number: 6358805Abstract: In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions.Type: GrantFiled: July 14, 1998Date of Patent: March 19, 2002Assignee: LG Semicon Co., Ltd.Inventors: Jeong-Hwan Son, Hyeong-Mo Yang
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Publication number: 20010019862Abstract: In a semiconductor device and method for manufacturing the same, a buried insulating layer is formed on a semiconductor substrate, multiple depletion regions of a first conductivity type are formed on the buried insulating layer and separated from one another, a field oxide layer is formed among the depletion regions of the buried insulating layer, a gate oxide layer is formed on the depletion regions, a gate is formed on the gate oxide layer, impurity regions that are heavily doped with impurities of a second conductivity type is formed in the depletion regions on both sides of the gate to define a source and drain, and a counter doping layer that is lightly doped with impurities of the second conductivity type is formed under the channel defined by a portion of the depletion regions positioned between the impurity regions.Type: ApplicationFiled: July 14, 1998Publication date: September 6, 2001Inventors: JEONG-HWAN SON, HYEONG-MO YANG
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Publication number: 20010010383Abstract: The present invention provides a semiconductor device that has reduced a short-channel effect by preventing the effective channel length at the sides of a channel of a transistor from decreasing by forming the length of a gate electrode to be different according to the parts. The semiconductor device according to the present invention includes a semiconductor substrate including active regions where a semiconductor device is to be fabricated and isolation regions for electrically isolating the active regions. A gate electrode is formed to go across the active region. A source and a drain are formed in the active region at both sides of the gate electrode, wherein the length of the gate electrode on the upper surface of the sides of the active region is longer than the length of the gate electrode of the center of the active region.Type: ApplicationFiled: January 23, 2001Publication date: August 2, 2001Applicant: Hyundai Electronics Industries Co., Ltd.Inventors: Jeong-Hwan Son, hyeong-Mo Yang