Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.

Abstract: According to the present technology, a storage device includes a nonvolatile storage area including a plurality of backup memory blocks each including a plurality of memory cells respectively connected to a plurality of word lines, and a controller configured to control the nonvolatile storage area to determine a target memory block in which data is to be stored among the plurality of backup memory blocks, determine a reference word line among the plurality of word lines coupled to the target memory block, and perform a pre-conditioning operation of programming dummy data to memory cells connected to at least one of remaining word lines except for the reference word line among the plurality of word lines coupled to the target memory block.

Abstract: A storage device includes a memory device including a plurality of memory dies; and a memory controller for addressing a memory die among the plurality of memory dies by using an address latch enable (ALE) signal and a command latch enable (CLE) signal, which are input during predetermined N cycles, where N is a natural number, and controlling the memory device such that the one memory die performs a memory operation. The memory controller may address the memory die by addressing a channel among a plurality of channels respectively connected to a plurality of package groups by using a chip enable (CE) signal.