Patents by Inventor Hyeong-Seok Yu

Hyeong-Seok Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11507960
    Abstract: A system for handling a lost item in an autonomous vehicle and a server. The vehicle includes a vision sensor configured to respectively capture a first vehicle interior image and a second vehicle interior image when a passenger boards and alights from the vehicle. The vehicle is configured to transmit the captured first vehicle interior image and second vehicle interior image to the server. The server is configured to compare the first vehicle interior image with the second vehicle interior image and transmit lost item information to the passenger when the lost item in the vehicle is sensed.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 22, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Eun Young Choi, Dong Il Yang, Jin Su Jeong, Ki Seok Seong, Min Sang Yu, Hyeong Jin Ham, Rosali Sun Pyun, Pil Cheon Jang, Woo Jin Kim
  • Patent number: 9842085
    Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeong-Seok Yu, Suk-Jin Kim
  • Patent number: 9354843
    Abstract: An apparatus and a method for generating a partial product for a polynomial operation are provided. The apparatus includes first encoders, each of the first encoders configured to selectively generate and output one of mutually exclusive values based on two inputs. The apparatus further includes a second encoder configured to generate and output two candidate partial products based on an output from a first one of the first encoders that is provided at a reference bit position of the inputs, an output from a second one of the first encoders that is provided at an upper bit position of the inputs, and a multiplicand. The apparatus further includes a multiplexer configured to select one of the candidate partial products output from the second encoder.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: May 31, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Seok Yu
  • Patent number: 9330057
    Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kwan Suh, Suk-Jin Kim, Hyeong-Seok Yu, Ki-Seok Kwon, Jae-Un Park
  • Patent number: 9135003
    Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kwan Suh, Hyeong-Seok Yu, Suk-Jin Kim
  • Patent number: 8874630
    Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: October 28, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyeong-Seok Yu, Suk-Jin Kim, Sang-Su Park, Yong-Surk Lee
  • Patent number: 8805904
    Abstract: Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand. The method may include generating 2n first functions by performing a logical operation on two input binary numbers on a bit-by-bit basis, calculating a second function by combining the first functions and a leading zero bit candidate value of the second function, and determining a final number of leading zero bits by recursively performing the calculating.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Seok Yu
  • Patent number: 8805915
    Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: August 12, 2014
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Hyeong-Seok Yu, Dong-Kwan Suh, Suk-Jin Kim, San Kim, Yong-Surk Lee
  • Publication number: 20140214913
    Abstract: An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas.
    Type: Application
    Filed: January 28, 2014
    Publication date: July 31, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeong-Seok YU, Suk-Jin KIM
  • Publication number: 20130226982
    Abstract: An apparatus and a method for generating a partial product for a polynomial operation are provided. The apparatus includes first encoders, each of the first encoders configured to selectively generate and output one of mutually exclusive values based on two inputs. The apparatus further includes a second encoder configured to generate and output two candidate partial products based on an output from a first one of the first encoders that is provided at a reference bit position of the inputs, an output from a second one of the first encoders that is provided at an upper bit position of the inputs, and a multiplicand. The apparatus further includes a multiplexer configured to select one of the candidate partial products output from the second encoder.
    Type: Application
    Filed: August 17, 2012
    Publication date: August 29, 2013
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Hyeong-Seok YU
  • Publication number: 20130151815
    Abstract: A reconfigurable processor includes a plurality of mini-cores and an external network to which the mini-cores are connected. Each of the mini-cores includes a first function unit including a first group of operation elements, a second function unit including a second group of operation elements that is different from the first group of operation elements, and an internal network to which the first function unit and the second function unit are connected.
    Type: Application
    Filed: December 11, 2012
    Publication date: June 13, 2013
    Inventors: Dong-Kwan Suh, Suk-Jin Kim, Hyeong-Seok Yu, Ki-Seok Kwon, Jae-Un Park
  • Publication number: 20120203811
    Abstract: Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand.
    Type: Application
    Filed: June 29, 2011
    Publication date: August 9, 2012
    Inventor: Hyeong-Seok Yu
  • Publication number: 20120124117
    Abstract: A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    Type: Application
    Filed: June 6, 2011
    Publication date: May 17, 2012
    Inventors: Hyeong-Seok Yu, Dong-Kwan Suh, Suk-Jin Kim, San Kim, Yong-Surk Lee
  • Publication number: 20120124116
    Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.
    Type: Application
    Filed: May 5, 2011
    Publication date: May 17, 2012
    Inventors: Hyeong-Seok YU, Suk-Jin Kim, Sang-Su Park, Yong-Surk Lee
  • Publication number: 20110219207
    Abstract: A reconfigurable processor for efficiently performing a vector operation, and a method of controlling the reconfigurable processor are provided. The reconfigurable processor designates at least one of a plurality of processing elements as a vector lane based on vector lane configuration information, and allocates a vector operation to the designated vector lane.
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kwan Suh, Hyeong-Seok Yu, Suk-Jin Kim
  • Publication number: 20070217389
    Abstract: Provided is an apparatus and method for processing data in a wireless network. The method includes receiving packet data transmitted in a downlink transmission interval, determining whether a current state is one in which processing of the packet data is possible; and if processing of the packet data is not possible, writing a pause bit for requesting hold of packet data transmission in a reserved bit of a Medium Access Control (MAC) header before transmission.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 20, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Woo Seo, Hyeong-Seok Yu, Jae-Kon Lee, Min-Young Ahn, Gang-Youl Yu
  • Publication number: 20070211808
    Abstract: Provided is an apparatus and method for calibrating an imbalance characteristic of a received signal of a frequency domain in a mobile receiver which supports an Orthogonal Frequency Division Multiplexing (OFDM) scheme. To this end, a received signal of a radio frequency band is converted into a baseband signal by using a carrier, and the baseband received signal is converted from a time domain signal to a frequency domain signal. Then, a calibration coefficient is measured by using two consecutively received signals from the Fast Fourier Transform (FFT) unit. An imbalance component included in the received signal of the frequency domain due to an imbalance of the carrier is removed by using the measured calibration coefficient. In this case, the two consecutively received signals refer to two transmission signals consecutively transmitted from a transmitter, and the two transmission signals are predetermined signals.
    Type: Application
    Filed: February 22, 2007
    Publication date: September 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Il Kang, Jae-Kon Lee, Hyeong-Seok Yu, Sang-Hyun Woo
  • Publication number: 20070214203
    Abstract: A dividing apparatus and method using coordinate rotation is disclosed. To this end, a plurality of rotation stages are sequentially performed until a divisor reaches a criterion and a rotation direction used in each of the plurality of stages is output. A division result acquired by performing rotation with respect to a dividend using the rotation direction for each of the plurality of stages is output.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 13, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeong-Seok Yu, Jae-Kon Lee, Chang-Woo Seo, Hyun-Il Kang
  • Publication number: 20070159162
    Abstract: Disclosed is a method and an apparatus for self-calibrating a Direct Current (DC) offset and an imbalance between orthogonal signals, which may occur in a mobile transceiver. In the apparatus, a transmitter of a mobile terminal functions as a signal generator, and a receiver of the mobile terminal functions as a response characteristic detector. Further, a baseband processor applies test signals to the transmitter, receives the test signals returning from the receiver, and compensates the imbalance and DC offset for the transmitter side and the receiver side by using the test signals. The test signal is applied to only one of the I channel path and the Q channel path, and an RF band signal output from the transmission side by the test signal is used as an input signal to the reception side.
    Type: Application
    Filed: December 8, 2006
    Publication date: July 12, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Il Kang, Jae-Kon Lee, Young-Hwan Lee, Hyeong-Seok Yu, Sang-Hyun Woo