Abstract: A thin film transistor array panel includes a first insulating substrate, a gate electrode positioned on the first insulating substrate, a gate insulating layer positioned on the gate electrode, a semiconductor layer positioned on the gate insulating layer, and a source electrode and a drain electrode positioned on the semiconductor layer and spaced apart from each other, in which the semiconductor layer includes three or more amorphous silicon layers having different bandgap energies from one another in order to reduce a leakage current and improve performance of a liquid crystal display.

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: A thin film transistor array panel includes a first insulating substrate, a gate electrode positioned on the first insulating substrate, a gate insulating layer positioned on the gate electrode, a semiconductor layer positioned on the gate insulating layer, and a source electrode and a drain electrode positioned on the semiconductor layer and spaced apart from each other, in which the semiconductor layer includes three or more amorphous silicon layers having different bandgap energies from one another in order to reduce a leakage current and improve performance of a liquid crystal display.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract: A transparent electrode for a display device includes a nanocarbon material and a dopant comprising at least one of aluminum, alumina, palladium, and gold. In some embodiments, the transparent electrode has excellent transparency and low resistance.

Abstract: A liquid crystal display includes: a substrate; a thin film transistor on the substrate; a pixel electrode which is connected to a terminal of the thin film transistor; a microcavity layer on the pixel electrode and including an injection hole through which material is provided to the microcavity layer; a supporting layer on the microcavity layer; and a capping layer on the supporting layer. The capping layer covers the injection hole, and the supporting layer includes silicon oxycarbide (SiOC).

Abstract: A method for manufacturing a display substrate includes forming a plastic base substrate. A blocking layer is formed on a surface of the plastic base substrate by depositing a first material and a second material that are distinct. A substrate includes a plastic base substrate and a blocking layer formed at surfaces of the plastic base substrate and having a first layer and a second layer alternatingly. The first layer and second layer include continuously changing component ratio of a first material to a second material. The blocking layer effectively blocks moisture and/or oxygen.

Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate.

Abstract: A thin film transistor includes a gate electrode on a substrate, a main active layer in electrical connection with the gate electrode and including an exposed channel portion, a source electrode in electrical connection with the main active layer, a drain electrode which is spaced apart from the source electrode and in electrical connection with the main active layer, and a sub active layer in electrical connection to the main active layer.

Abstract: A thin film transistor array panel includes: an substrate; a gate line positioned on the substrate; a data line intersecting the gate line; a thin film transistor connected to the gate line and the data line; a gate insulating layer between the gate electrode of the thin film transistor and the semiconductor of the thin film transistor; a pixel electrode connected to the thin film transistor; and a passivation layer positioned between the pixel electrode and the thin film transistor, wherein at least one of the gate insulating layer and the passivation layer includes a silicon nitride layer, and the silicon nitride layer includes hydrogen content at less than 2×1022 cm3 or 4 atomic %.

Abstract: Disclosed herein is a polycrystalline silicon solar cell, including: a back electrode formed on a transparent insulating substrate; an N-type polycrystalline silicon layer in which amorphous silicon is crystallized through MIC process, and in which electrons are accumulated; a light-absorbing layer which is formed by vertically crystallizing an intrinsic amorphous silicon layer using the polycrystalline silicon layer as a seed for crystallization through MIVC process, in which pairs of electrons and holes are generated in response to incident light, and which has a vertical column grain structure in which grains are arranged in the direction in which electrons and holes move; a P-type polycrystalline silicon layer which has the vertical column grain structure, and in which holes are accumulated; a transparent electrode layer; front electrodes; and an antireflection coating film, and is a method of fabricating the same.

Abstract: Disclosed herein is a method of forming a light-absorbing layer of a polycrystalline silicon solar cell, including: forming a polycrystalline silicon layer on a back electrode; forming an intrinsic amorphous silicon layer on the polycrystalline silicon layer; and heat-treating the transparent insulating substrate to vertically crystallize the intrinsic amorphous silicon layer using the polycrystalline silicon layer as a seed for crystallization through a metal induced vertical crystallization (MIVC) process to form the intrinsic amorphous silicon layer into a light-absorbing layer made of polycrystalline silicon, and is a method of fabricating a high-efficiency polycrystalline silicon solar cell using the light-absorbing layer.

Abstract: A thin-film transistor (“TFT”) substrate includes a metal wiring including copper or a copper alloy on a substrate, an inorganic layer on an upper surface and side surfaces of the metal wiring to surround the metal wiring, the inorganic layer in direct contact with the metal wiring, and a planarization layer on the inorganic layer and in direct contact with the inorganic layer.

Abstract: A planar light source device includes a lower substrate, a cathode electrode a carbon nanotube, an upper substrate, a fluorescent layer, and an anode electrode. The cathode electrode is on the lower substrate. The carbon nanotube is electrically connected to the cathode electrode. The upper substrate faces the lower substrate. The fluorescent layer and the anode electrode are formed on the upper substrate. Therefore, the planar light source device generates light without using mercury.

Abstract: A backlight includes a cold cathode fluorescent lamp, a container for receiving the same and a liquid crystal display, device having the container. The lamp includes a lamp tube, a first electrode having a first end disposed inside the lamp tube and a second end disposed outside the lamp tube and a second electrode plated on an outer surface of the lamp tube. The cold cathode fluorescent lamp is easily coupled/separated to/from the container having a clip type power-supplying module in a clip-coupling manner. In addition, a shock absorbing member is installed at the clip type power-supplying module so as to absorb an impact applied to the cold cathode fluorescent lamp.

Abstract: A thin film transistor substrate includes a substrate including a display area and a peripheral area surrounding the display area, gate lines formed on the substrate including gate electrodes, an auxiliary insulating layer formed on the gate lines, a gate insulating layer formed on the auxiliary insulating layer and the gate lines, a semiconductor layer formed on the gate insulating layer, data lines formed on the semiconductor layer including source electrodes and drain electrodes, a passivation layer formed on the data lines, pixel electrodes formed on the passivation layer and electrically connected to the drain electrode, wherein the boundary line of the auxiliary insulating layer is located at or within the boundary of the gate line.

Abstract: A planar light source device includes a lower substrate, a cathode electrode a carbon nanotube, an upper substrate, a fluorescent layer, and an anode electrode. The cathode electrode is on the lower substrate. The carbon nanotube is electrically connected to the cathode electrode. The upper substrate faces the lower substrate. The fluorescent layer and the anode electrode are formed on the upper substrate. Therefore, the planar light source device generates light without using mercury.

Abstract: A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate comprising a three mask process. The 3 mask process comprising, forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming a first, second, and third passivation film successively on the substrate.

Abstract: A planar light source device includes a lower substrate, a cathode electrode a carbon nanotube, an upper substrate, a fluorescent layer, and an anode electrode. The cathode electrode is on the lower substrate. The carbon nanotube is electrically connected to the cathode electrode. The upper substrate faces the lower substrate. The fluorescent layer and the anode electrode are formed on the upper substrate. Therefore, the planar light source device generates light without using mercury.