Abstract: Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Abstract: A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.

Abstract: The present invention relates to a transistor for providing protection from electrostatic discharge when a semiconductor device is exposed to electrostatic state, the transistor for providing protection from Electrostatic Discharge(ESD) being characterized by the fact that in case the gate length of a transistor is L, the gate length at the edges of the transistor is longer than the gate length L, and that the gate length is fixed as L and the edge of the transistor, in which the gate is adjacent to the active regions, has a grooved shape with an acute angle, and also the present invention makes the high-intensity electric field alleviated, and also enables the current to flow uniformly over the overall gate, and the heating effect is prevented, resulting in a prolonged life expectancy of the device.

Abstract: An electrostatic discharge protection circuit comprising a first transistor formed on a semiconductor substrate adjacently to one side of an insulation oxide film region, for transferring a voltage from a first voltage terminal to an output terminal in response to a first input signal, a second transistor formed on the semiconductor substrate adjacently to the other side of the insulation oxide film region, for transferring a voltage form a second input signal, and an NPN transistor having its collector connected to the first voltage terminal, its emitter connected to the output terminal and its base connected to a bulk region of the second transistor. According to the present invention, when a semiconductor device is exposed to electrostatic discharge, the electrostatic discharge protection circuit discharges charges introduced by the electrostatic discharge before they are discharge through an internal circuitry.