Abstract: A device may include an amplifying transistor configured to amplify a radio frequency signal when powered by a supply signal and biased by a biasing signal. The device may include a biasing circuit configured to control the biasing signal based on a level of the supply signal, the biasing circuit including a reference transistor which is mirrored with the amplifying transistor to control a current flowing through the amplifying transistor such as to compensate a gain variation of the amplifier assembly.

Abstract: Power amplifier supply networks with harmonic terminations are disclosed. In certain embodiments, a power amplifier system includes a first power amplifier that amplifies a first radio frequency (RF) signal of a first fundamental frequency, a second power amplifier that amplifies a second RF signal of a second fundamental frequency, and a power amplifier supply network that distributes a power amplifier supply voltage to the first power amplifier at a first distribution node and to the second power amplifier at a second distribution node. The power amplifier supply network includes a first harmonic termination circuit connected to the first distribution node that provide an open circuit at about twice the first fundamental frequency, and a second harmonic termination circuit connected to the second distribution node and that provides an open circuit at about twice the fundamental frequency.

Abstract: Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Abstract: Front-end for processing 2G signal using 3G/4G paths. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Abstract: Circuits and methods for 2G amplification using 3G/4G linear path combination. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Abstract: Circuits and methods for 2G amplification using 3G/4G linear path combination. In some embodiments, a front-end architecture can include a first amplification path and a second amplification path, with each being configured to amplify a 3G/4G signal, and the first amplification path including a phase shifting circuit. The front-end architecture can further include a splitter configured to receive a 2G signal and split the 2G signal into the first and second amplification paths, and a combiner configured to combine amplified 2G signals from the first and second amplification paths into a common output path. The front-end architecture can further include an impedance transformer implemented along the common output path to provide a desired impedance for the combined 2G signal.

Abstract: An apparatus and a method for eliminating distortion component from the output of power amplifier, comprising a baseband linearization arrangement for receiving the baseband signal, demodulating a distorted amplifier output signal, comparing the received baseband signal with the demodulated amplification output signal for providing a predistorted signal to remove the distorted component of the amplifier output signal applied by the power amplifier, and a carrierband linearization amplification arrangement for amplifying the output signal of the baseband linearization arrangement in order to linearize the distorted component of the amplifier output signal using the predistorted signal and for further linearizing the distorted component from the output of the power amplifier by extracting an error signal and amplifying the error signal to be combined the amplifier output signal in order to eliminate any distorted components in the amplifier output signal.