Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

Abstract: A data transmitting device and a flat plate display using the same are disclosed. The data transmitting device includes a clock generator to generate and output a first clock signal and to generate a plurality of second clocks signals having different phases; a serializer to convert parallel image data and a dot clock input at a slow speed to high speed serial data and high speed clock according to the first and second clocks outputted from the clock generator and to output the high speed serial image data and the high speed clock; and a signal converter to convert the serial image data and the high speed clock outputted from the serializer into differential signals and to output the differential signals.

Abstract: A Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes a Sample-and-Hold Amplifier (SHA) for sampling and holding an externally input analog voltage, a comparator for comparing a level of the sampled and held analog voltage with a level of an analog signal corresponding to n bits and generating a comparison signal according to result of comparison, an SAR logic circuit for sequentially generating a digital signal from a Most significant Bit (MSB) to a Least Significant Bit (LSB) in response to the comparison signal, a Digital-to-Analog Converter (DAC) for providing the analog signal to the comparator, and an output register for holding the sequentially generated digital signal from the MSB to the LSB to generate an n-bit digital signal, wherein, upon externally receiving a start signal, the SAR logic circuit generates a digital signal of a MSB having a one-bit phase delay compared with the start signal.

Abstract: A method and apparatus for detecting jitter of a Phase Locked Loop (PLL), which is capable of detecting a jitter level of the PLL without using a separate jitter measurement device, is disclosed.

Abstract: A method and apparatus for detecting jitter of a Phase Locked Loop (PLL), which is capable of detecting a jitter level of the PLL without using a separate jitter measurement device, is disclosed.

Abstract: A data transmitting device and a flat plate display using the same are disclosed. The data transmitting device includes a clock generator to generate and output a first clock signal and to generate a plurality of second clocks signals having different phases; a serializer to convert parallel image data and a dot clock input at a slow speed to high speed serial data and high speed clock according to the first and second clocks outputted from the clock generator and to output the high speed serial image data and the high speed clock; and a signal converter to convert the serial image data and the high speed clock outputted from the serializer into differential signals and to output the differential signals.

Abstract: Disclosed is a device of stepwise eliminating an offset voltage in an analog-to-digital pipeline converter. The device includes a sub analog-to-digital converter to convert an input signal inputted from a preceding stage into a first digital signal, a sub digital-to-analog converter to convert the first digital signal into a first analog signal, and an offset removing unit to remove a part of the offset voltage according to an offset code relative to the offset voltage based on a remaining signal to thereby generate a corrected remaining signal.

Abstract: A camera having a camera finder system including a finder housing having a camera finder. The camera further includes a movable housing linearly movable into the finder housing whereby the camera finder is moved forward out of a camera body or backward into the finder housing of the camera; and drive device for linearly moving the movable housing.