Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.

Abstract: A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

Abstract: A semiconductor device includes a peripheral circuit structure, a semiconductor layer, a source conductive layer, a connecting mold layer, a support conductive layer, a buried insulating layer, a gate stack structure, a mold structure, a channel structure and a supporter through the gate stack structure, a THV through the mold structure and the buried insulating layer, a dam structure between the gate stack structure and the mold structure, an upper supporter layer on the dam structure, and a word line separation layer through the gate stack structure and the upper supporter layer. The dam structure includes a first spacer, a second spacer inside the first spacer, a lower supporter layer connected to the upper supporter layer and partially on or covering an inner side wall of the second spacer, and an air gap with a side wall defined by the second spacer and a top end defined by the lower supporter layer.

Abstract: A semiconductor device includes a substrate, gate electrodes stacked in a first direction, channel structures penetrating through the gate electrodes, a horizontal conductive layer below the gate electrodes on the substrate, separation regions penetrating through the gate electrodes and the horizontal conductive layer, and extending in the first and second directions, a cell region insulating layer covering the gate electrodes, and an upper support layer on the separation regions and the cell region insulating layer and having openings to overlap the separation regions. Each of the separation regions includes a contact conductive layer and a first separation insulating layer in a trench, and has first regions below the openings and second regions alternating with the first regions. The contact conductive layer is in contact with the substrate in the first regions, and is spaced apart from the substrate by the first separation insulating layer in the second regions.

Abstract: A semiconductor device comprises a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure; and a memory vertical structure, separation structures, and support vertical structures penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and intermediate gate layers, wherein the separation structures include a first separation structure, wherein the support vertical structures include a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layers, and the upper gate layer, and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure on the same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure on the same level as the lower gate layer.

Abstract: A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.

Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.

Abstract: A vertical memory device includes a gate electrode structure formed on a substrate including a cell array region and a pad region, a channel, contact plugs, and support structures. The gate electrode structure includes gate electrodes extending in a second direction and stacked in a staircase shape in a first direction on the pad region. The channel extends through the gate electrode structure on the cell array region. The contact plugs contact corresponding ones of steps, respectively, of the gate electrode structure. The support structures extend through the corresponding ones of the steps, respectively, and extend in the first direction on the pad region. The support structure includes a filling pattern and an etch stop pattern covering a sidewall and a bottom surface thereof. An upper surface of each of the support structures is higher than that of the channel.