Patents by Inventor Hyeon-Ok Jung

Hyeon-Ok Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180175143
    Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.
    Type: Application
    Filed: December 6, 2017
    Publication date: June 21, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chan-sic YOON, Ki-seok Lee, Ki-wook Jung, Dong-oh Kim, Ho-in Lee, Je-min Park, Seok-han Park, Augustin Hong, Ju-yeon Jang, Hyeon-ok Jung, Yu-jin Seo
  • Patent number: 9634012
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Publication number: 20170025420
    Abstract: In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
    Type: Application
    Filed: February 4, 2016
    Publication date: January 26, 2017
    Inventors: Tae-Jin Park, Chan-sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung, Dae-Ik Kim, Bong-Soo Kim, Yong-Kwan Kim, Eun-Jung Kim, Se-Myeong Jang, Min-su Choi, Sung-Hee Han, Yoo-Sang Hwang
  • Patent number: 9478548
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: October 25, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Yeong Lee, Chan-Sic Yoon, Ki-Seok Lee, Hyeon-Ok Jung
  • Patent number: 9461051
    Abstract: An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: October 4, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Min Park, Seok-Hyun Lim, Tae-Yong Song, Hyun-Chul Yoon, Yoo-Sang Hwang, Hyeon-Ok Jung
  • Publication number: 20160035731
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.
    Type: Application
    Filed: March 5, 2015
    Publication date: February 4, 2016
    Inventors: DO-YEONG LEE, CHAN-SIC YOON, KI-SEOK LEE, HYEON-OK JUNG
  • Publication number: 20160027787
    Abstract: An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
    Type: Application
    Filed: September 8, 2015
    Publication date: January 28, 2016
    Inventors: Je-Min Park, Seok-Hyun Lim, Tae-Yong Song, Hyun-Chul Yoon, Yoo-Sang Hwang, Hyeon-Ok Jung
  • Publication number: 20140374809
    Abstract: An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed.
    Type: Application
    Filed: December 13, 2013
    Publication date: December 25, 2014
    Inventors: Je-Min Park, Seok-Hyun Lim, Tae-Yong Song, Hyun-Chul Yoon, Yoo-Sang Hwang, Hyeon-Ok Jung