Abstract: There is provided a low-resolution imaging apparatus configured to form and transmit a low-resolution image of an object. The low-resolution imaging apparatus includes: a low-resolution camera configured to form the low-resolution image of the object; a microcontroller including an analog-to-digital convertor (ADC) that converts the low-resolution image into a digital image; an energy harvesting module configured to provide power to the low-resolution camera and the microcontroller; and a radio frequency identification (RFID) unit configured to transmit the digital-converted low-resolution image.

Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: Provided is an Al—Fe-alloy plated steel sheet for hot forming, having excellent TWB welding characteristics since excellent hardness uniformity of a TWB weld zone after hot forming is obtained by suitably controlling a batch annealing condition, after plating Al, such that an Al—Fe-alloy layer is formed; a hot forming member; and manufacturing methods therefor.

Abstract: A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.

Abstract: A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.

Abstract: A display device includes a driving transistor; a transistor connected to the driving transistor; a first insulating layer; a first data conductive layer including a first connection pattern; a second insulating layer including a lower via hole; a second data conductive layer including a second connection pattern connected to the first connection pattern and a first conductive line; a third insulating layer including an intermediate via hole; a third data conductive layer including a third connection pattern connected to the second connection pattern, a second conductive line extending in a second direction, and a first data line which extends in the second direction; a fourth insulating layer including an upper via hole; and a light emitting element disposed including a first electrode, wherein at least two of the lower via hole, the intermediate via hole, and the upper via hole overlap each other in a third direction.

Abstract: A display device including a light-emitting element, an encapsulation layer over the light-emitting element and including a first inorganic encapsulation layer, an organic encapsulation layer and a second inorganic encapsulation layer in order, and the first inorganic encapsulation layer and the second inorganic encapsulation layer in direct contact with each other to define an inorganic encapsulation area of the display device, a supply voltage line electrically connected to the light-emitting element, a signal line which provides an electrical signal to the display area, and within the inorganic encapsulation area of the display device, the signal line overlapping the supply voltage line and an etch stop pattern between the supply voltage line and the signal line which overlap each other.

Abstract: A display device having a display area including a plurality of pixels arranged along a first direction and a second direction, and a non-display area located around the display area, the non-display area including a first peripheral area surrounding the display area, a second peripheral area located at a lower side of the first peripheral area, and a bending area located between the first and second peripheral areas, the display device comprises a base substrate; a multiplexer circuit unit in the second peripheral area on the base substrate, the multiplexer circuit unit being spaced apart from the display area with the bending area interposed therebetween; spider lines connected to the multiplexer circuit unit and the plurality of pixels; data lines connected to the pixel disposed in the display area on the base substrate and extending along the second direction; and connection lines connecting the data line to the spider line.

Abstract: A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.

Abstract: A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.

Abstract: A display device includes a first transistor including a gate electrode, a second transistor including a lower gate electrode, an upper gate electrode, and a first end portion electrically connected to an end portion of the first transistor, a lower gate signal line extending in a first direction, an upper gate signal line disposed on the lower gate signal line and extending in a first direction, and a first connection pattern disposed on the upper gate signal line, electrically connecting the gate electrode and a second end portion of the second transistor, and intersecting the lower gate signal line and the upper gate signal line. An entirety of the upper gate signal line overlaps a part of the lower gate signal line in an overlapping area in which the lower gate signal line or the upper gate signal line overlaps the first connection pattern.