Abstract: A storage system and an operating method of the same are provided. A storage system may comprise, a host device including processing circuitry, a storage device configured to communicate with the host device, and the processing circuitry is configured to, generate a test power fault based on power fault setting information stored in a setting value table, and inject the test power fault into the storage device based on the power fault setting information.

Abstract: A characteristic data pre-processing system includes a data acquisition device that collects characteristic data including first cell distribution data defined according to first default read levels, and second cell distribution data defined according to second default read levels, a data pre-processing apparatus that merges the first cell distribution data and the second cell distribution data according crop ranges to generate training data, wherein the crop ranges are defined according to the first default levels and the second default levels, and a database that stores the training data communicated from the data pre-processing apparatus.

Abstract: A characteristic data pre-processing system includes a data acquisition device that collects characteristic data including first cell distribution data defined according to first default read levels, and second cell distribution data defined according to second default read levels, a data pre-processing apparatus that merges the first cell distribution data and the second cell distribution data according crop ranges to generate training data, wherein the crop ranges are defined according to the first default levels and the second default levels, and a database that stores the training data communicated from the data pre-processing apparatus.

Abstract: A method of determining a read voltage of a memory device includes performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish between a pair of adjacent logic states of memory cells in the first group of storage regions, detecting a read voltage level, among the different read voltages, at which a minimum number of erroneous bits is generated in the at least one read operation, and determining a read voltage for a second group of storage regions to which a second error correction rate is applied, based on the detected read voltage level, wherein the first error correction rate is higher than the second error correction rate.

Abstract: A method of determining a read voltage of a memory device comprises performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish between a pair of adjacent logic states of memory cells in the first group of storage regions, detecting a read voltage level, among the different read voltages, at which a minimum number of erroneous bits is generated in the at least one read operation, and determining a read voltage for a second group of storage regions to which a second error correction rate is applied, based on the detected read voltage level, wherein the first error correction rate is higher than the second error correction rate.