Abstract: Integrated circuit memory devices include sense amplifier arrays having layouts that are configured to support greater pitch between adjacent input/output lines, while maintaining high levels of integration density. A sense amplifier array is provided having first and second column select I/O blocks that are arranged in an alternating zig-zag layout sequence, with the first column select I/O blocks positioned in a first row of the sense amplifier array and the second column select I/O blocks positioned in a second row of the sense amplifier array. The sense amplifier array also includes an alternating zig-zag layout sequence of first and second N-type (or P-type) sense amplifier blocks that extends back-and-forth between the first and second rows. The zig-zag layout sequence of sense amplifier blocks is interleaved with the zig-zag layout sequence of the column select I/O blocks.

Abstract: Integrated circuit memory devices include sense amplifier arrays having layouts that are configured to support greater pitch between adjacent input/output lines, while maintaining high levels of integration density. A sense amplifier array is provided having first and second column select I/O blocks that are arranged in an alternating zig-zag layout sequence, with the first column select I/O blocks positioned in a first row of the sense amplifier array and the second column select I/O blocks positioned in a second row of the sense amplifier array. The sense amplifier array also includes an alternating zig-zag layout sequence of first and second N-type (or P-type) sense amplifier blocks that extends back-and-forth between the first and second rows. The zig-zag layout sequence of sense amplifier blocks is interleaved with the zig-zag layout sequence of the column select I/O blocks.

Abstract: A sense amplifier of a semiconductor memory device has increased driving capability and can reduce the size of a memory device. The sense amplifier includes a pull-up sense amplifier and a pull-down sense amplifier which are connected between a bit line and a complementary bit line to sense data stored in a memory cell, and a pull-up sense driver and a pull-down sense driver each of includes an NMOS transistor. The sense amplifier can reduce the sensing time between the pull-up and pull-down sense drivers starting to operate and a column select line being enabled. The sense amplifier also reduces the time necessary for restoring or refreshing the data or charge in the capacitor of a memory cell after the sensing operation.

Abstract: The present invention includes a plurality of memory cells store information and one row decoder for every four word lines to decode an external address output a single row decoding signal. A word drive decoder generates a word line driving signal. A split word line driver arranged such that the memory cell array is formed between each split word line driver, inputs the single row decoding signal output from the row decoder and the word line driving signal output from the word drive decoder to thereby output a word line signal to select appropriate memory cells. With this structure, the reduced number of metalized lines requiring straps which overlay the memory cell array help minimize short-circuit problems that would otherwise occur when dimensions of metalized lines are reduced.

Abstract: A semiconductor memory device with a memory array of cells formed as a matrix has bit lines, and word lines driven by word line drivers, where each of the word line drivers simultaneously selects and drives at least two word lines in order to minimize line resistances of the word lines, thereby minimizing a delay time and improving a speed of sensing a cell data. Accordingly a number of the word line drivers is at least one-half a number of the word lines.

Abstract: A semiconductor memory device with a memory array of cells formed as a matrix has bit lines, and word lines driven by word line drivers, where each of the word line drivers simultaneously selects and drives at least two word lines in order to minimize line resistances of the word lines, thereby minimizing a delay time and improving a speed of sensing a cell data. Accordingly a number of the word line drivers is at least one-half a number of the word lines.