Abstract: A stand-off pad, and method of fabricating the same, for supporting a workpiece in a spaced apart relation to a workpiece support chuck. More specifically, the wafer stand-off pad is fabricated of a polymeric material, such as polyimide, which is disposed upon the support surface of the chuck. The stand-off pad maintains a wafer, or other workpiece, in a spaced apart relation to the support surface of the chuck. The distance between the underside surface of the wafer and the chuck is defined by the thickness of the stand-off pad. This distance should be larger than the expected diameter of contaminant particles that may lie on the surface of the chuck. In this manner, the contaminant particles do not adhere to the underside of the wafer during processing and the magnitude of the chucking voltage is maintained between the workpiece and the chuck.

Abstract: A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.

Abstract: A process for fabricating an electrostatic chuck (20) comprising the steps of (c) forming a base (80) having an upper surface with cooling grooves (85) therein, the grooves sized and distributed for holding a coolant therein for cooling the base; and (d) pressure conforming an electrical insulator layer (45) to the grooves on the base by the steps of (i) placing the base into a pressure forming apparatus (25) and applying an electrical insulator layer over the grooves in the base; and (ii) applying a sufficiently high pressure onto the insulator layer to pressure conform the insulator layer to the grooves to form a substantially continuous layer of electrical insulator conformal to the grooves on the base.

Abstract: An electrostatic chuck (20) for holding a substrate (75) comprises (i) a base (80) having an upper surface (95) with grooves (85) therein, the grooves (85) sized and distributed for holding coolant for cooling a substrate (75), and (ii) a substantially continuous insulator film (45) conformal to the grooves (85) on upper surface (95) of the base (80). The base (80) can be electrically conductive and capable of serving as the electrode (50) of the chuck (20), or the electrode (50) can be embedded in the insulator film (45). The insulator film (45) has a dielectric breakdown strength sufficiently high that when a substrate (75) placed on the chuck (20) and electrically biased with respect to the electrode (50), electrostatic charge accumulates in the substrate (75) and in the electrode (50) forming an electrostatic force that attracts and holds the substrate (75) to the chuck (20).

Abstract: A puncture resistant electrostatic chuck (20) is described. The chuck (20) comprises at least one electrode (25); and a composite insulator (30) covering the electrode. The composite insulator comprises a matrix material having a conformal holding surface (50) capable of conforming to the substrate (35) under application of an electrostatic force generated by the electrode to reduce leakage of heat transfer fluid held between the substrate and the holding surface. A hard puncture resistant layer, such a layer of fibers or an aromatic polyamide layer, is positioned below the holding surface (50) and is sufficiently hard to increase the puncture resistance of the composite insulator.

Abstract: A plasma etch reactor and a related method of its operation to provide self-cleaning of its top electrode, which is subject to being coated by polymer deposits during normal operation. In one form of the invention, radio-frequency (rf) power is applied to the top electrode on a continuous basis, but at a much lower power level than that of a primary rf power source used to supply power through a lower electrode, to generate and sustain a plasma in the reactor. The small rf power applied through the top electrode is selected to be of such a level as to remove deposits from the electrode continuously, as they are formed, but without removing any significant amount of electrode material. In another form of the invention, power is applied to the top electrode periodically during cleaning periods and power supply to the lower electrode is suspended during the cleaning periods.

Abstract: The invention is embodied in a method of determining an optimum de-chucking voltage for nullifying residual electrostatic forces on a wafer in an electrostatic chuck for removal of the wafer from the chuck, including holding the wafer on the electrostatic chuck by applying an electrostatic potential to the chuck, introducing a gas between the wafer and the chuck, reducing the electrostatic potential of the chuck while observing a rate of leakage of the gas from between the wafer and the chuck, and recording as the optimum dechucking voltage the value of the electrostatic potential obtaining when the rate of leakage exceeds a predetermined threshold.

Abstract: Insulation between first and second levels of aluminum metallization in semiconductor integrated circuit structures comprises a plasma planarized, deposited silicon dioxide layer and another silicon dioxide layer deposited upon said plasma planarized layer.

Abstract: A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.

Abstract: For optimal performance, the threshold voltages V.sub.TP and V.sub.TN of the p- and n-channel transistors in a CMOS device should be the respective complements of each other. In polysilicon-gate devices, this can be achieved by adjusting the corresponding gate-metal work function utilizing p.sup.+ and n.sup.+ polysilicon for the respective gates of the p- and n-channel transistors. However, when a refractory metal silicide-over-polysilicon gate structure is employed in a VLSI CMOS device in which the gates of a pair of adjacent complementary transistors are connected together, an anomalously large negative V.sub.TP is measured.The invention is a unique process sequence that achieves substantially complementary p- and n-channel transistor thresholds in a high-speed VLSI CMOS device that includes silicide-over-polysilicon gates.

Abstract: It has been found that stress in X-ray transparent films used to form masks for X-ray lithography also cause distortions of the film and of the high-resolution X-ray-absorptive pattern formed thereon. A method is disclosed which anneals boron nitride films for use in X-ray masks in such a way as to control stress.

Abstract: A method for fabricating a device which includes a tantalum silicide structure, and which is essentially free of conductive etch residues, is disclosed. The method includes the steps of depositing tantalum and silicon onto a substrate, patterning the tantalum and silicon, and then sintering the patterned tantalum and silicon to form a patterned layer of tantalum silicide.

Abstract: In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Abstract: In a plasma-assisted etching apparatus and method designed to pattern aluminum or polysilicon, surfaces in the reaction chamber are coated with a layer of aluminum oxide. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Abstract: In order to form MOSFET structures, a cobalt layer (16) is deposited and sintered, at about 400.degree. C. to 500.degree. C., on a patterned semiconductor wafer having exposed polycrystalline (14) or monocrystalline (11) silicon portions, as well as exposed oxide (15 or 25) portions. The cobalt reacts with exposed surfaces of the silicon portions and forms thereat such compounds as cobalt monosilicide (CoSi) or di-cobalt silicide (C0.sub.2 Si), or a mixture of both. The unreacted cobalt is selectively removed, as by selective etching in a suitable acid bath. A heat treatment at about 700.degree. C. or more, preferably in an oxidizing ambient which contains typically about 2 percent oxygen, converts the cobalt compound(s) into relatively stable cobalt disilicide (CoSi.sub.2).

Abstract: In the patterning of an organic layer on a VLSI wafer by means of reactive oxygen (or other) ion anisotropic etching, build-ups of oxides (or other compounds) on the sidewalls of apertures formed in the organic layer are removed prior to etching the material, typically aluminum, of the VLSI wafer located at the bottom of these apertures, using the patterned organic layer as an etch mask.

Abstract: The efficient production of sequential layers of silicon dioxide and polycrystalline silicon is possible using a specific set of reaction steps. This set of reaction steps includes the oxidation of silicon at low oxygen pressure and at temperatures of the magnitude of 900 degrees C., followed by the deposition of polycrystalline silicon at substantially the same temperature utilizing a dichloride silane chemical vapor deposition (CVD) process.

Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.

Abstract: In a charged-particle-beam lithographic system, charge accumulation on the workpiece during alignment or writing can cause significant pattern placement errors. A film (16) formed directly under the resist layer (56) to be patterned is utilized as a charge-conducting medium during lithography. The pattern delineated in the resist layer (56) is transferred into the film (16) and subsequently into an underlying layer (20). The film (16) is highly compatible with standard lithographic and etching processes used to fabricate LSI and VLSI circuits.

Abstract: The compounds TiSi.sub.2 and TaSi.sub.2 have been found to be suitable substitutes for polysilicon layers in semiconductor integrated circuits. Suitable conducting properties of the compounds are ensured by providing a relatively thin substrate of polysilicon.