Abstract: A method of modeling damages to a crystal caused by an incident particle includes obtaining particle information and crystal information; estimating energy loss of the incident particle based on the particle information and the crystal information; estimating a volume of a vacancy based on the energy loss; estimating a vacancy reaction based on the crystal information and the volume of the vacancy; and generating output data based on the vacancy reaction, the output data including quantification data of the damages.

Abstract: A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes.

Abstract: Discussed herein is a method of managing product reception/release data of a refrigerator including obtaining internal image data of the refrigerator using a camera provided in the refrigerator, extracting high-reliability data from the internal image data of the refrigerator, updating product reception/release data based on the high-reliability data, and creating a user database based on the updated product reception/release data.

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

Abstract: A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.

Abstract: According to an embodiment of the present disclosure, a refrigerator may include a storage compartment, an outer door, one or more cameras provided in the outer door, a global DB configured to store a plurality of default food identification items and a plurality of default product names respectively corresponding to the plurality of default food identification items, and a local DB configured to store edited product names and a food identification item corresponding to the edited product names, and a processor configured to photograph an internal image of the storage compartment through the one or more cameras, obtain a food identification item from the photographed internal image, determine whether the obtained food identification item is stored in the local DB, and when the food identification item is not stored in the local DB, determine whether the obtained food identification item is stored in the global DB.

Abstract: An image sensor is provided. The image sensor includes a first semiconductor chip including a first semiconductor substrate having a pixel unit, a first wiring structure having a first wiring layer, and a first bonding pad; a second semiconductor chip including a second semiconductor substrate having first and second surfaces, a second wiring structure on the first surface, contacting the first wiring structure, and having a second wiring layer, a second upper bonding pad bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface; a bonding layer including a bonding insulating layer on the second surface, and a second lower bonding pad connected to the via structure; and a third semiconductor chip including a third semiconductor substrate, a third wiring structure contacting the bonding insulating layer, and a third bonding pad bonded to the second lower bonding pad.

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

Abstract: A computer-implemented method includes obtaining a labeled data set of images including data from a rehearsal memory and new input data, augmenting the labeled data set to generate a first data set and a second data set, wherein each image of the first data set corresponds to a corresponding image of the second data set, inputting the first data set into a query encoder and inputting the second data set into a momentum encoder to obtain encodings output by the query encoder and the momentum encoder, obtaining a contrastive loss based on the encodings using a sum of a first contrastive loss function and a second contrastive loss function, updating parameters of the query encoder based on the obtained contrastive loss, and updating parameters of the momentum encoder based on parameters of the query encoder.

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

Abstract: A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

Abstract: An embodiment of the present invention provides, comprising: a communication unit configured to communicate with a plurality of external AI apparatuses; and a processor configured to receive sound signals of the user from the plurality of external AI apparatuses, calculate a distance and a variation of the distance from each of the plurality of external AI apparatuses to the user based on the received sound signals, determine a current path of the user based on the calculated distance and the calculated variation of the distance, and determine a future path of the user based on the current path.

Abstract: An embodiment of the present invention provides an artificial intelligence (AI) apparatus for recognizing a speech of a user, the artificial intelligence apparatus includes a memory to store a speech recognition model and a processor to obtain a speech signal for a user speech, to convert the speech signal into a text using the speech recognition model, to measure a confidence level for the conversion, to perform a control operation corresponding to the converted text if the measured confidence level is greater than or equal to a reference value, and to provide feedback for the conversion if the measured confidence level is less than the reference value.

Abstract: A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.