Abstract: Aspects of the technical idea of the inventive concept provide a semiconductor package including a semiconductor package module, a semiconductor device provided below the semiconductor package module, a redistribution layer between the semiconductor package module and the semiconductor device, and an encapsulation material surrounding the semiconductor package module, on the redistribution layer, wherein the semiconductor package module includes a base chip, a plurality of memory chips disposed on the base chip, and a sealing material sealing the plurality of memory chips on the base chip, each of the plurality of memory chips includes a first semiconductor substrate, a first active layer on a lower surface of the first semiconductor substrate, and a first through electrode extending through the first semiconductor substrate.

Abstract: An artificial intelligence device according to an embodiment of the present disclosure may comprise a memory configured to store a plurality of action plan templates; and at least one processor configured to: obtain a command and an initial image, obtain an action plan template among the plurality of action plan templates based on the obtained command and initial image, generate a robot control command from the command, the initial image and the obtained action plan template, and control both arms of a robot through the generated robot control command.

Abstract: A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

Abstract: The present disclosure relates to an artificial intelligence apparatus capable of classifying and detecting an item of an unseen class having high visual similarity to an item of a seen class that has been learned and known in advance, and a method for detecting an unseen class items thereof, and when the item image is input, generate encoded data by encoding the item image, generate decoded data by decoding the encoded data using a codebook of a plurality of codebooks in which encoded data for each item class is stored, corresponding to a pre-learned item class, and detect the unknown item by classifying the class of the item image based on the generated decoded data.

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

Abstract: A semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first group of the upper pads and a second group of the upper pads; a buffer layer covering a side surface of the first group of the upper pads; and an insulating layer surrounding a side surface of the second group of the upper pads and a side surface of the buffer layer on the substrate, wherein the buffer layer includes a first material having a first Young's modulus smaller than a second Young's modulus of a second material in the plurality of upper pads.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

Abstract: A cooking device according to an embodiment of the present disclosure can comprise: a cooking chamber; a heating unit configured to heat the cooking chamber; a camera configured to photograph a food located inside the cooking chamber; a user input unit configured to receive a user input; and a processor configured to: identify a type of the food from a food image photographed by the camera, obtain visual attribute information indicating a cooking state of the food from the user input, and control the heating unit to cook the food based on cooking information matched to the type of food and the visual attribute information.

Abstract: The present disclosure relates to semiconductor packages and methods of fabricating the semiconductor packages. An example semiconductor package includes a first semiconductor die including a first substrate and a first bonding layer on the first substrate, a second semiconductor die disposed on the first semiconductor die, the second semiconductor die including a second substrate and a second bonding layer under the second substrate, and a silicon oxide layer interposed between the first semiconductor die and the second semiconductor die, where at least one pore is disposed in the silicon oxide layer, and the at least one pore has a height of 1 ? to 2 nm.

Abstract: A semiconductor package includes a redistribution structure, a lower semiconductor device arranged on the redistribution structure and including first through electrodes each having a first horizontal width, a connecting substrate arranged on the redistribution structure and spaced apart from the lower semiconductor device in a horizontal direction and including second through electrodes each having a second horizontal width greater than the first horizontal width, a first molding layer arranged on the redistribution structure and surrounding a side surface of the lower semiconductor device and a side surface of the connecting substrate, and an upper semiconductor device arranged on the lower semiconductor device and the connecting substrate, the upper semiconductor device electrically connected to the first and second through electrodes.

Abstract: Discussed herein is a method of managing product reception/release data of a refrigerator including obtaining internal image data of the refrigerator using a camera provided in the refrigerator, extracting high-reliability data from the internal image data of the refrigerator, updating product reception/release data based on the high-reliability data, and creating a user database based on the updated product reception/release data.

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

Abstract: A semiconductor package includes a package substrate, a lower semiconductor device arranged on the package substrate and including first through electrodes, first lower connection bumps arranged between the package substrate and the lower semiconductor device and electrically connecting the package substrate to the first through electrodes, a connecting substrate arranged on the package substrate and including second through electrodes, second lower connection bumps arranged between the package substrate and the connecting substrate and electrically connecting the package substrate to the second through electrodes, and an upper semiconductor device arranged on the lower semiconductor device and electrically connected to the first through electrodes and the second through electrodes.

Abstract: A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.

Abstract: According to an embodiment of the present disclosure, a refrigerator may include a storage compartment, an outer door, one or more cameras provided in the outer door, a global DB configured to store a plurality of default food identification items and a plurality of default product names respectively corresponding to the plurality of default food identification items, and a local DB configured to store edited product names and a food identification item corresponding to the edited product names, and a processor configured to photograph an internal image of the storage compartment through the one or more cameras, obtain a food identification item from the photographed internal image, determine whether the obtained food identification item is stored in the local DB, and when the food identification item is not stored in the local DB, determine whether the obtained food identification item is stored in the global DB.

Abstract: An image sensor is provided. The image sensor includes a first semiconductor chip including a first semiconductor substrate having a pixel unit, a first wiring structure having a first wiring layer, and a first bonding pad; a second semiconductor chip including a second semiconductor substrate having first and second surfaces, a second wiring structure on the first surface, contacting the first wiring structure, and having a second wiring layer, a second upper bonding pad bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface; a bonding layer including a bonding insulating layer on the second surface, and a second lower bonding pad connected to the via structure; and a third semiconductor chip including a third semiconductor substrate, a third wiring structure contacting the bonding insulating layer, and a third bonding pad bonded to the second lower bonding pad.