Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

Abstract: A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.

Abstract: An image sensor is provided. The image sensor includes a first semiconductor chip including a first semiconductor substrate having a pixel unit, a first wiring structure having a first wiring layer, and a first bonding pad; a second semiconductor chip including a second semiconductor substrate having first and second surfaces, a second wiring structure on the first surface, contacting the first wiring structure, and having a second wiring layer, a second upper bonding pad bonded to the first bonding pad, and a via structure connected to the second wiring layer and extending to the second surface; a bonding layer including a bonding insulating layer on the second surface, and a second lower bonding pad connected to the via structure; and a third semiconductor chip including a third semiconductor substrate, a third wiring structure contacting the bonding insulating layer, and a third bonding pad bonded to the second lower bonding pad.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.

Abstract: The present invention provides a long non-coding RNA (lncRNA) biomarker composition in serum exosomes, comprising LOC105377989, LOC105375434, LOC107986997, and LOC101927073, for diagnosing atrial fibrillation on the basis of the results of profile analysis of lncRNA in serum exosomes of patients with atrial fibrillation. When used, the lncRNA biomarker composition enables non-invasive in-vitro diagnosis, and exhibits an excellent effect in atrial fibrillation diagnosis, and thus is highly applicable as a useful diagnostic biomarker for atrial fibrillation.

Abstract: Provided are a semiconductor package having a structure in which semiconductor devices are stacked on an interposer to reduce thermal stress, increase an adhesive force of an underfill, and reduce the size of the package, and a method of manufacturing the semiconductor package. The semiconductor package includes a package substrate, an interposer disposed on the package substrate and connected to the package substrate through a first connection terminal and a first underfill, a first semiconductor device disposed on the interposer and connected to the interposer through a second connection terminal and a second underfill, and a sealing material disposed on the interposer and sealing a first semiconductor device. A part of a side surface of the second underfill is exposed from a side surface of the sealing material.

Abstract: Discussed herein is a method of managing product reception/release data of a refrigerator including obtaining internal image data of the refrigerator using a camera provided in the refrigerator, extracting high-reliability data from the internal image data of the refrigerator, updating product reception/release data based on the high-reliability data, and creating a user database based on the updated product reception/release data.

Abstract: Aspects of the technical idea of the inventive concept provide a semiconductor package including a semiconductor package module, a semiconductor device provided below the semiconductor package module, a redistribution layer between the semiconductor package module and the semiconductor device, and an encapsulation material surrounding the semiconductor package module, on the redistribution layer, wherein the semiconductor package module includes a base chip, a plurality of memory chips disposed on the base chip, and a sealing material sealing the plurality of memory chips on the base chip, each of the plurality of memory chips includes a first semiconductor substrate, a first active layer on a lower surface of the first semiconductor substrate, and a first through electrode extending through the first semiconductor substrate.

Abstract: An artificial intelligence device according to an embodiment of the present disclosure may comprise a memory configured to store a plurality of action plan templates; and at least one processor configured to: obtain a command and an initial image, obtain an action plan template among the plurality of action plan templates based on the obtained command and initial image, generate a robot control command from the command, the initial image and the obtained action plan template, and control both arms of a robot through the generated robot control command.

Abstract: A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

Abstract: A semiconductor package includes a first semiconductor chip including a first substrate and a first bonding layer disposed on the first substrate, and having a flat first outer surface provided by the first bonding layer; and a second semiconductor chip disposed on the first outer surface of the first semiconductor chip, including a second substrate and a second bonding layer disposed on the second substrate, and having a flat second outer surface provided by the second bonding layer and contacting the first outer surface of the first semiconductor chip. The first bonding layer includes a first outermost insulating layer providing the first outer surface, a first internal insulating layer stacked between the first outermost insulating layer and the first substrate, first external marks disposed in the first outermost insulating layer and spaced apart from each other, and first internal marks interlaced with the first external marks within the first internal insulating layer.

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

Abstract: The present disclosure relates to an artificial intelligence apparatus capable of classifying and detecting an item of an unseen class having high visual similarity to an item of a seen class that has been learned and known in advance, and a method for detecting an unseen class items thereof, and when the item image is input, generate encoded data by encoding the item image, generate decoded data by decoding the encoded data using a codebook of a plurality of codebooks in which encoded data for each item class is stored, corresponding to a pre-learned item class, and detect the unknown item by classifying the class of the item image based on the generated decoded data.

Abstract: A semiconductor package may include a redistribution substrate, a first semiconductor chip on the redistribution substrate, and a second semiconductor chip between the redistribution substrate and the first semiconductor chip. The second semiconductor chip may have a width in a first direction that is smaller than a width of the first semiconductor chip in the first direction. The first semiconductor chip may include a first alignment key pattern on a bottom surface thereof. The second semiconductor chip may be spaced apart from the first alignment key pattern. The second semiconductor chip may include a second interconnection layer on the bottom surface of the first semiconductor chip, a second semiconductor substrate on a bottom surface of the second interconnection layer and exposing a bottom surface of an edge region of the second interconnection layer, and a second alignment key pattern on the edge region of the second interconnection layer.

Abstract: A method of manufacturing a semiconductor package includes preparing a wafer structure having a first semiconductor substrate and a plurality of first front surface connection pads. A lower semiconductor chip having a preliminary semiconductor substrate and a plurality of second front surface connection pads are attached to the wafer structure such that the plurality of first front surface connection pads and the plurality of second front surface connection pads correspond to each other. A plurality of bonding pads is formed by bonding together the plurality of first front surface connection pads and the plurality of second front surface connection pads corresponding to each other. A second semiconductor substrate having a horizontal width that is less than that of the second wiring structure is formed by removing a portion of the preliminary semiconductor substrate.

Abstract: A semiconductor chip includes: a substrate; a plurality of upper pads on the substrate, the plurality of upper pads including a first group of the upper pads and a second group of the upper pads; a buffer layer covering a side surface of the first group of the upper pads; and an insulating layer surrounding a side surface of the second group of the upper pads and a side surface of the buffer layer on the substrate, wherein the buffer layer includes a first material having a first Young's modulus smaller than a second Young's modulus of a second material in the plurality of upper pads.

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first semiconductor chip, a second semiconductor chip on a top surface of the first semiconductor chip and having a width less than that of the first semiconductor chip, and a molding layer on the first semiconductor chip and surrounding the second semiconductor chip. The first semiconductor chip includes a first semiconductor substrate and a first circuit layer on a top surface of the first semiconductor substrate. The first semiconductor substrate includes a first part adjacent to the top surface of the first semiconductor substrate and a second part adjacent to a bottom surface of the first semiconductor substrate. The first and second parts include the same semiconductor material. The first part has a single crystalline structure. The second part may have a polycrystalline structure.

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

Abstract: A cooking device according to an embodiment of the present disclosure can comprise: a cooking chamber; a heating unit configured to heat the cooking chamber; a camera configured to photograph a food located inside the cooking chamber; a user input unit configured to receive a user input; and a processor configured to: identify a type of the food from a food image photographed by the camera, obtain visual attribute information indicating a cooking state of the food from the user input, and control the heating unit to cook the food based on cooking information matched to the type of food and the visual attribute information.