Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.

Abstract: A semiconductor device having a spacer with an air gap is manufactured by forming a first conductive pattern over a semiconductor substrate; forming a spacer on sidewalls of the first conductive pattern; forming a sacrifice layer on sidewall of the spacer, the sacrifice layer having a different etching selectivity with the spacer; forming a second conductive pattern to fill a space between the first conductive pattern and the first conductive pattern; and forming an air gap between the first and second conductive patterns by selectively removing the sacrifice layer.

Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.

Abstract: A buried gate in a semiconductor device and a method for fabricating the same are presented. The method includes: forming a gate trench in an active region of a semiconductor substrate; filling the gate trench with a barrier metal film and a metal film; recessing the metal film and the barrier metal film to form buried gate electrodes that partially fill the gate trench; recessing the barrier metal film of the buried gate electrode below the surface of the metal film; and filling an exposed part of the buried gate electrode and the gate trench with a capping film.

Abstract: An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

Abstract: A method for manufacturing a semiconductor device having a metal silicide layer comprises forming a structure including a plurality of gate stacks formed on a semiconductor substrate, forming a gate spacer layer formed on an upper surface of the semiconductor substrate and around a sidewall of each gate stack, and forming an insulation layer between the gate stacks. The method further comprises forming a metal silicide layer on an exposed surface of the semiconductor substrate between the gate stacks.

Abstract: An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

Abstract: A method for manufacturing a semiconductor device having a metal silicide layer comprises forming a structure including a plurality of gate stacks formed on a semiconductor substrate, forming a gate spacer layer formed on an upper surface of the semiconductor substrate and around a sidewall of each gate stack, and forming an insulation layer between the gate stacks. The method further comprises forming a metal silicide layer on an exposed surface of the semiconductor substrate between the gate stacks.

Abstract: Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

Abstract: Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

Abstract: Disclosed is a method for fabricating a semiconductor device with a dual gate dielectric structure. The method includes the steps of: sequentially forming a first oxide layer, a nitride layer and a second oxide layer on a substrate provided with a cell region for the NVDRAM and a peripheral circuit region for a logic circuit; forming a mask on the cell region; performing a first wet etching process by using the mask as an etch barrier to remove the second oxide layer formed in the peripheral circuit region; performing a second wet etching process by using the second oxide layer remaining in the cell region as an etch barrier to remove the nitride layer formed in the peripheral circuit region; forming a third oxide layer on the first oxide layer remaining in the peripheral circuit region; and forming a gate electrode on the second oxide layer and the third oxide layer.

Abstract: A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.

Abstract: A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.