Patents by Inventor Hyo Gi JO

Hyo Gi JO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11940599
    Abstract: An optical imaging system includes a first lens having a convex image-side surface, a second lens having a concave object-side surface, a third lens, a fourth lens, and a fifth lens disposed sequentially from an object side. The optical imaging system satisfies 4.8<f/IMG_HT<9.0, where f is a focal length of the optical imaging system, and IMG_HT is half a diagonal length of an imaging surface of an image sensor.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 26, 2024
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ju Hwa Son, Jong Gi Lee, Hyo Jin Hwang, Sang Hyun Jang, Yong Joo Jo
  • Publication number: 20220165648
    Abstract: Disclosed is a semiconductor package including a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first surface of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second surface of the semiconductor chip; a conductive post disposed outside the semiconductor chip; a first redistribution structure, which is on the first surface of the semiconductor chip and includes a first redistribution insulation layer supporting the conductive stud and the conductive post; a second redistribution structure, which is on the second surface of the semiconductor chip and includes a second redistribution insulation layer disposed on the adhesive layer; and a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 26, 2022
    Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATION
    Inventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba
  • Publication number: 20220148993
    Abstract: Provided is a semiconductor package including a first semiconductor chip having a bottom surface adjacent to a first active layer and an top surface opposite to the bottom surface; a first adhesive layer disposed on the top surface of the first semiconductor chip; a first conductive stud disposed on the bottom surface of the first semiconductor chip and electrically connected to the first active layer; a first conductive post disposed outside the first semiconductor chip; a redistribution structure disposed under the first semiconductor chip and including a redistribution pattern connected to the first conductive stud and the first conductive post and a redistribution insulation layer surrounding the redistribution pattern; and a molding layer surrounding the first semiconductor chip, the first adhesive layer, the first conductive stud, and the first conductive post on the redistribution structure.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 12, 2022
    Applicants: NEPES CO., LTD., NEPES LAWEH CORPORATION
    Inventors: Byung Cheol KIM, Yong Tae KWON, Hyo Gi JO, Dong Hoon OH, Jae Cheon LEE, Hyung Jin SHIN, Mary Maye Melgo Galimba