Patents by Inventor Hyo Seob Yoon
Hyo Seob Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9935267Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: GrantFiled: April 8, 2016Date of Patent: April 3, 2018Assignee: SK Hynix Inc.Inventors: Min Seok Kim, Hyo Seob Yoon
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Patent number: 9859493Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: GrantFiled: April 8, 2016Date of Patent: January 2, 2018Assignee: SK Hynix Inc.Inventors: Min Seok Kim, Hyo Seob Yoon
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Publication number: 20160225989Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Inventors: Min Seok KIM, Hyo Seob YOON
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Publication number: 20160225985Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Inventors: Min Seok KIM, Hyo Seob YOON
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Patent number: 9337420Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: GrantFiled: October 4, 2013Date of Patent: May 10, 2016Assignee: SK Hynix Inc.Inventors: Min Seok Kim, Hyo Seob Yoon
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Publication number: 20150207068Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.Type: ApplicationFiled: April 1, 2015Publication date: July 23, 2015Inventors: Han Woo CHO, Hyo Seob YOON, Yong Seok LEE
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Patent number: 9024291Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.Type: GrantFiled: August 26, 2013Date of Patent: May 5, 2015Assignee: SK Hynix Inc.Inventors: Han Woo Cho, Hyo Seob Yoon, Yong Seok Lee
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Publication number: 20150090951Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.Type: ApplicationFiled: January 16, 2014Publication date: April 2, 2015Applicant: SK hynix Inc.Inventors: Min Seok KIM, Hyo Seob YOON
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Patent number: 8975689Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The method includes sequentially depositing a gate electrode material and a sacrificial insulating layer on a semiconductor substrate, patterning the gate electrode material and the sacrificial insulating layer to form one or more holes exposing a surface of the semiconductor substrate, forming a gate insulating layer on an inner sidewall of the hole, forming one or more pillar patterns each filled in the hole and recessed on a top thereof, forming a contact unit and an electrode unit on the pillar pattern, removing a patterned sacrificial insulating layer and forming a spacer nitride material on the semiconductor substrate from which the patterned sacrificial insulating layer is removed, and removing portions of the spacer nitride material and a patterned gate electrode material between the pillar patterns.Type: GrantFiled: January 16, 2014Date of Patent: March 10, 2015Assignee: SK Hynix Inc.Inventors: Min Seok Kim, Hyo Seob Yoon
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Publication number: 20140374683Abstract: A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole, A variable resistance material layer may be formed in the second hole to contact the lower electrode and an upper electrode may be formed in the first hole to contact the variable resistance material layer.Type: ApplicationFiled: October 4, 2013Publication date: December 25, 2014Applicant: SK hynix Inc.Inventors: Min Seok KIM, Hyo Seob YOON
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Patent number: 8916949Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.Type: GrantFiled: December 18, 2012Date of Patent: December 23, 2014Assignee: SK Hynix Inc.Inventors: Hyo Seob Yoon, Han Woo Cho
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Publication number: 20140319445Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.Type: ApplicationFiled: August 26, 2013Publication date: October 30, 2014Applicant: SK hynix Inc.Inventors: Han Woo CHO, Hyo Seob YOON, Yong Seok LEE
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Publication number: 20140061571Abstract: A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.Type: ApplicationFiled: December 18, 2012Publication date: March 6, 2014Applicant: SK hynix Inc.Inventors: Hyo Seob Yoon, Han Woo Cho
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Patent number: 8384056Abstract: A phase change random access memory includes a semiconductor substrate, a switching device pattern formed on the semiconductor substrate, a bottom electrode contact pattern formed on the switching device pattern, a phase change layer pattern formed on the bottom electrode contact pattern, and an insulating layer disposed at a portion of an contact surface between the bottom electrode contact pattern and the phase change layer pattern.Type: GrantFiled: July 20, 2010Date of Patent: February 26, 2013Assignee: Hynix Semiconductor Inc.Inventors: Min Seok Kim, Hyo Seob Yoon
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Publication number: 20110073830Abstract: A phase change random access memory includes a semiconductor substrate, a switching device pattern formed on the semiconductor substrate, a bottom electrode contact pattern formed on the switching device pattern, a phase change layer pattern formed on the bottom electrode contact pattern, and an insulating layer disposed at a portion of an contact surface between the bottom electrode contact pattern and the phase change layer pattern.Type: ApplicationFiled: July 20, 2010Publication date: March 31, 2011Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Min Seok KIM, Hyo Seob YOON
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Patent number: 7741671Abstract: Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof.Type: GrantFiled: January 22, 2009Date of Patent: June 22, 2010Assignee: Hynix Semiconductor Inc.Inventors: Pyeong Won Oh, Woo Jin Kim, Hoon Jung Oh, Hyo Gun Yoon, Hyo Seob Yoon, Baik II Choi
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Patent number: 7655535Abstract: A method for fabricating a device isolation structure of a semiconductor device includes the steps of forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, etching a portion of the pad nitride layer, the pad oxide layer and the semiconductor substrate to form a trench, forming a sidewall oxide layer over the sidewalls of the trench; removing the sidewall oxide layer in the dummy region, forming a silicon nitride layer over the sidewalls of the sidewall oxide layer both in the cell region and in the dummy region, filling the trench with an insulating layer, polishing the insulating layer to expose the pad nitride layer, and removing the pad nitride layer.Type: GrantFiled: December 29, 2006Date of Patent: February 2, 2010Assignee: Hynix Semiconductor Inc.Inventors: Hyo Seob Yoon, Woo Jin Kim, Ok Min Moon, Ji Yong Park
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Publication number: 20090122461Abstract: Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof.Type: ApplicationFiled: January 22, 2009Publication date: May 14, 2009Applicant: Hynix Semiconductor Inc.Inventors: Pyeong Won OH, Woo Jin Kim, Hoon Jung Oh, Hyo Gun Yoon, Hyo Seob Yoon, Baik II Choi
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Patent number: 7498628Abstract: Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof.Type: GrantFiled: August 25, 2005Date of Patent: March 3, 2009Assignee: Hynix Semiconductor Inc.Inventors: Pyeong Won Oh, Woo Jin Kim, Hoon Jung Oh, Hyo Gun Yoon, Hyo Seob Yoon, Baik Il Choi
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Patent number: RE43765Abstract: A method for fabricating a device isolation structure of a semiconductor device includes the steps of forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, etching a portion of the pad nitride layer, the pad oxide layer and the semiconductor substrate to form a trench, forming a sidewall oxide layer over the sidewalls of the trench; removing the sidewall oxide layer in the dummy region, forming a silicon nitride layer over the sidewalls of the sidewall oxide layer both in the cell region and in the dummy region, filling the trench with an insulating layer, polishing the insulating layer to expose the pad nitride layer, and removing the pad nitride layer.Type: GrantFiled: January 31, 2012Date of Patent: October 23, 2012Assignee: Hynix Semiconductor Inc.Inventors: Hyo Seob Yoon, Woo Jin Kim, Ok Min Moon, Ji Yong Park