Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

Abstract: A semiconductor device is provided including a resistor structure on a semiconductor substrate. The resistor structure includes pad portions and a resistor body connecting the pad portions. The pad portions each have a width greater than a width of the resistor body. The pad portions each include a pad pattern and a liner pattern covering a sidewall and a lower surface of the pad pattern. The resistor body extends laterally from the liner pattern. The pad pattern includes a different material from the resistor body and the liner pattern.

Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

Abstract: A semiconductor chip includes: a gate pattern on a substrate; an interlayer insulation layer on the gate pattern; a first wiring structure on the interlayer insulation layer; and a defect detection circuit electrically connected to the gate pattern and the first wiring structure. The first wiring structure is electrically connected to the gate pattern via a contact plug through the interlayer insulation layer. The defect detection circuit is electrically connected to the gate pattern and the first wiring structure, and the defect detection circuit is configured to detect defects in the first wiring structure and at least one of the gate pattern and the substrate.

Abstract: A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.