Patents by Inventor Hyo-sig Won
Hyo-sig Won has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10621300Abstract: A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.Type: GrantFiled: October 25, 2017Date of Patent: April 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Patent number: 10430546Abstract: A computer-implemented method compresses placing standard cells based on design data defining an integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which a first pattern, a second pattern, and a third pattern in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a non-transitory computer-readable storage medium. The space constraints define minimum spaces between the first pattern, the second pattern, and the third pattern. A color violation does not occur between the first pattern, second pattern, and the third pattern. A first mask, a second mask, and a third mask are generated based on the layout. A semiconductor device is manufactured by using the generated first mask, the second mask, and the third mask.Type: GrantFiled: November 3, 2017Date of Patent: October 1, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Patent number: 10418354Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.Type: GrantFiled: May 16, 2018Date of Patent: September 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Min Ryu, Hyo-Sig Won
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Patent number: 10340263Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.Type: GrantFiled: September 28, 2017Date of Patent: July 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyo Sig Won, Chan Uk Shin, Kwang Ok Jeong, Kwon Chil Kang
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Publication number: 20180261590Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.Type: ApplicationFiled: May 16, 2018Publication date: September 13, 2018Inventors: SEONG-MIN RYU, Hyo-Sig Won
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Publication number: 20180173838Abstract: A computer-implemented method. Standard cells are placed based on design data defining the integrated circuit (IC). A layout of the IC is generated by performing colorless routing, by which first through third patterns in a triple patterning lithography (TPL) layer are arranged on the placed standard cells. The arrangement is based on space constraints. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first through third patterns. A color violation does not occur between the first through third patterns. First, second, and third masks are generated based on the layout. A semiconductor device is manufactured by using the generated first, second, and third masks.Type: ApplicationFiled: November 3, 2017Publication date: June 21, 2018Inventors: Hyo-Sig Won, Myung-Soo Jang, Hyoun-Soo Park, Da-Yeon Cho
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Publication number: 20180173837Abstract: A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.Type: ApplicationFiled: October 25, 2017Publication date: June 21, 2018Inventors: HYO-SIG WON, MYUNG-SOO JANG, HYOUN-SOO PARK, DA-YEON CHO
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Publication number: 20180166432Abstract: An integrated circuit includes a plurality of power rail pairs and a circuit chain. Each of the plurality of power rail pairs includes one of a plurality of high power rails configured to provide a first power supply voltage and one of a plurality of low power rails configured to provide a second power supply voltage that is lower than the first power supply voltage. The circuit chain includes a plurality of unit circuits that are cascade-connected such that an output of a previous unit circuit is provided as an input of a next unit circuit. The plurality of unit circuits are connected distributively to the plurality of power rail pairs.Type: ApplicationFiled: September 28, 2017Publication date: June 14, 2018Inventors: HYO SIG WON, CHAN UK SHIN, KWANG OK JEONG, KWON CHIL KANG
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Patent number: 9991249Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.Type: GrantFiled: January 31, 2017Date of Patent: June 5, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seong-Min Ryu, Hyo-Sig Won
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Patent number: 9852252Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.Type: GrantFiled: July 16, 2015Date of Patent: December 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Tae-joong Song, Jae-ho Park, Gi-young Yang, Jin-tae Kim, Hyo-sig Won
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Patent number: 9837437Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: GrantFiled: June 2, 2017Date of Patent: December 5, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
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Publication number: 20170271367Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: ApplicationFiled: June 2, 2017Publication date: September 21, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-hoon BAEK, Sang-kyu OH, Jung-Ho DO, Sun-young PARK, Seung-young LEE, Hyo-sig WON
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Publication number: 20170236814Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.Type: ApplicationFiled: January 31, 2017Publication date: August 17, 2017Inventors: SEONG-MIN RYU, HYO-SIG WON
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Patent number: 9716106Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: GrantFiled: August 9, 2016Date of Patent: July 25, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
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Publication number: 20160351583Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: ApplicationFiled: August 9, 2016Publication date: December 1, 2016Applicant: Samsung Electronics Co., Ltd.Inventors: Sang-hoon BAEK, Sang-kyu Oh, Jung-Ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
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Patent number: 9431383Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: GrantFiled: July 16, 2015Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-hoon Baek, Sang-kyu Oh, Jung-ho Do, Sun-young Park, Seung-young Lee, Hyo-sig Won
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Publication number: 20160055284Abstract: A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region.Type: ApplicationFiled: July 16, 2015Publication date: February 25, 2016Inventors: Sang-hoon Baek, Tae-joong Song, Jae-ho Park, Gi-young Yang, Jin-tae Kim, Hyo-sig Won
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Publication number: 20160027769Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.Type: ApplicationFiled: July 16, 2015Publication date: January 28, 2016Inventors: Sang-hoon BAEK, Sang-kyu OH, Jung-ho DO, Sun-young PARK, Seung-young LEE, Hyo-sig WON
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Patent number: 8659316Abstract: A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.Type: GrantFiled: September 5, 2012Date of Patent: February 25, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyung Ock Kim, Jae Han Jeon, Jung Yun Choi, Hyo Sig Won, Kyu Myung Choi
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Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices
Patent number: 8621399Abstract: In a method of designing a semiconductor device, a transistor included in a layout of the semiconductor device may be selected. A biasing data may be set for changing a characteristic of the selected transistor. A design rule check (DRC) process for the layout of the semiconductor device may be performed after ignoring the biasing data. An optical proximity correction (OPC) process for the layout of the semiconductor device may be performed based on the biasing data.Type: GrantFiled: April 27, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Kyung-Tae Do, Yong-Seok Lee, Hyo-Sig Won, Jung-Yun Choi, Jong-Ho Kim