Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract: A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.

Abstract: Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads.

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate, a semiconductor chip, bonding wires, and a molding film. The package substrate includes a first surface having a recessed portion, a second surface opposed to the first surface, an opening extending from the recessed portion of the first surface to the second surface, and bonding pads provided on the first surface. The semiconductor chip is disposed on the second surface of the package substrate to cover the opening, and includes center pads exposed through the opening. Bonding wires electrically connect the center pads and the bonding pads through the opening. The molding film covers the bonding pads, the center pads, and the bonding wires. A depth of the recessed portion is greater than a distance between the recessed portion of the first surface and a lowermost surface of the molding film.

Abstract: A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group.

Abstract: A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device.

Abstract: A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.

Abstract: A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device.

Abstract: A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

Abstract: Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads.

Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

Abstract: A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.