Abstract: The present invention relates to a nail sticker which is curable by ultraviolet ray and the lower surface of the nail sticker before being cured by the ultraviolet ray includes a curved surface that the center of the nail sticker is upwardly curved.

Abstract: A multilayer electronic component according to an example embodiment of the present disclosure may include: a body including a dielectric layer and internal electrodes; external electrodes disposed on the third and fourth surfaces; and side margin portions disposed on the fifth and sixth surfaces, and the cover portion and the side margin portion may include titanium (Ti) and gallium (Ga), and a ratio (B/A) of the number of moles (B) of gallium (Ga) compared to 100 moles of titanium (Ti) included in the side margin portion to the number of moles (A) of gallium (Ga) compared to 100 moles of titanium (Ti) included in the cover portion may satisfy 1.5?B/A.

Abstract: A multilayer electronic component includes: a body including a capacitance formation portion including a dielectric layer and internal electrodes alternately disposed with the dielectric layer in a first direction, and a cover portion disposed on upper and bottom surfaces of the capacitance formation portion in the first direction; and an external electrode disposed on the body, and the cover portion may include titanium (Ti), gallium (Ga), and phosphorus (P), and a molar amount of gallium (Ga) with respect to 100 moles of titanium (Ti) included in the cover portion may be 0.3 moles or more and 6.0 moles or less.

Abstract: The present invention relates to a nail sticker and the nail sticker is a curable nail sticker. The nail sticker includes a soft layer, the soft layer includes a resin for the soft layer, and the resin for the soft layer may include at least one of cellulose acetate butyrate and cellulose acetate propionate.

Abstract: A multilayer electronic component includes a body including a capacitance forming portion including a dielectric layer and an internal electrode alternately disposed in a first direction, and cover portions disposed on both end surfaces of the capacitance forming portion in the first direction, respectively, and including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction, and a fifth surface and a sixth surface opposing each other in a third direction; external electrodes disposed on the third and fourth surfaces of the body, respectively; and side margin portions disposed on the fifth and sixth surfaces of the body, respectively. At least one of the capacitance forming portion, the cover portion, or the side margin portions includes a secondary phase including gallium (Ga).

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

Abstract: A multilayer capacitor includes: a body including dielectric layers and internal electrodes alternately disposed therein; and external electrodes disposed on the body and connected to the internal electrodes, respectively. Each of the internal electrodes includes a Ni grain, ceramics distributed in the Ni grain, a first coating layer surrounding the Ni grain, and second coating layers surrounding the ceramics.

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

Abstract: A multilayer capacitor includes: a body including dielectric layers and internal electrodes alternately disposed therein; and external electrodes disposed on the body and connected to the internal electrodes, respectively. Each of the internal electrodes includes a Ni grain, ceramics distributed in the Ni grain, a first coating layer surrounding the Ni grain, and second coating layers surrounding the ceramics.

Abstract: A multilayer ceramic electronic component includes an inner layer part comprising dielectric layers and internal electrodes that are alternately disposed; and cover parts disposed on upper and lower surfaces of the inner layer part. The cover parts contain a nickel metal.

Abstract: A multilayer ceramic electronic component includes an inner layer part comprising dielectric layers and internal electrodes that are alternately disposed; and cover parts disposed on upper and lower surfaces of the inner layer part. The cover parts contain a nickel metal.

Abstract: A multilayer ceramic electronic component includes an inner layer part comprising dielectric layers and internal electrodes that are alternately disposed; and cover parts disposed on upper and lower surfaces of the inner layer part. The cover parts contain a nickel metal.

Abstract: There is provided a nickel powder for internal electrodes satisfying the following equation: 0.8?b*D*?/6?1.0 wherein a specific surface area of the nickel powder is defined as b, an average particle size of the nickel powder is defined as D, and a density of the nickel powder is defined as ?.

Abstract: There are provided a conductive paste for internal electrodes, a multilayer ceramic electronic component including the same, and a method of manufacturing the same. The conductive paste for internal electrodes including: a nickel (Ni) powder; a nickel oxide (NiO) powder having a content of 5.0 to 15.0 parts by weight based on 100 parts by weight of the nickel powder; and an organic vehicle.

Abstract: There are provided a conductive paste for internal electrodes, a multilayer ceramic electronic component including the same, and a method of manufacturing the same. The conductive paste for internal electrodes including: a nickel (Ni) powder; a nickel oxide (NiO) powder having a content of 5.0 to 15.0 parts by weight based on 100 parts by weight of the nickel powder; and an organic vehicle.

Abstract: There are provided a nickel powder for an internal electrode, synthesized by a vapor phase synthesis method using plasma, more particularly, a nickel powder for an internal electrode, having a favorable crystallite diameter and high density, a method of producing the same, and a multilayer ceramic electronic component including the same. According to the nickel powder for an internal electrode, the method of producing the same, and the multilayer ceramic electronic component including the same, a nickel powder having less impurities, a favorable crystallite diameter, and high density can be produced.

Abstract: A method for synthesizing nano particles, including: moving material in a plasma generating space in a first direction; and synthesizing nano particles by cooling the material moved along the first direction, wherein the synthesizing the nano particles may be performed by cooling the material at gradually lower temperatures during the moving thereof in the first direction.

Abstract: Disclosed herein is an apparatus for synthesizing nano particles. The apparatus for synthesizing nano particles is configured to include: a plasma generator that generates plasma; a recovery device that recovers the synthesized nano particles; and a cooler that is disposed between the plasma generator and the recovery device and includes a cooling path where the nano particles are synthesized, while material supplied from the plasma generator is cooled, wherein the cooling path is set to have lower cooling temperatures for each section as going to the moving direction of the nano particles.