Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

Abstract: The present invention relates to a nail sticker and the nail sticker is a curable nail sticker. The nail sticker includes a soft layer, the soft layer includes a resin for the soft layer, and the resin for the soft layer may include at least one of cellulose acetate butyrate and cellulose acetate propionate.

Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

Abstract: A semiconductor memory device includes a substrate having a cell array area and a core area near the cell array area, the cell array area including a direct contact hole exposing an active region, a buried contact in the cell array area, the buried contact being connected to a storage element, a direct contact in the cell array area, the direct contact including an upper layer and a lower layer, the upper layer including a metal, and the lower layer being in the direct contact hole in direct contact with the active region and including a silicide of the metal, bit lines in contact with the upper layer of the direct contact, and word lines crossing the bit lines.

Abstract: A multilayer electronic component includes a body including a capacitance forming portion including a dielectric layer and an internal electrode alternately disposed in a first direction, and cover portions disposed on both end surfaces of the capacitance forming portion in the first direction, respectively, and including a first surface and a second surface opposing each other in the first direction, a third surface and a fourth surface opposing each other in a second direction, and a fifth surface and a sixth surface opposing each other in a third direction; external electrodes disposed on the third and fourth surfaces of the body, respectively; and side margin portions disposed on the fifth and sixth surfaces of the body, respectively. At least one of the capacitance forming portion, the cover portion, or the side margin portions includes a secondary phase including gallium (Ga).

Abstract: A semiconductor device may include a substrate including a cell block region and a peripheral region, which are adjacent to each other in a first direction, an active pattern on the cell block region, a bit line provided on the active pattern and extended in the first direction, a first insulating structure in contact with the bit line, and a contact plug electrically connected to the bit line. The bit line may include a first curved portion, a first linear portion connected to the first curved portion, and a first intervening portion connected to the first curved portion. The contact plug may be overlapped with the first curved portion.

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Abstract: A semiconductor memory device and a method of fabricating a semiconductor memory device, the device including a first impurity region in a substrate; a first bit line that crosses over the substrate and is connected to the first impurity region; a bit-line contact between the first bit line and the first impurity region; and a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer.

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: A semiconductor device includes a substrate, a first impurity implantation region and a second impurity implantation region on the substrate and spaced apart from each other, a storage node contact in contact with the first impurity implantation region, the storage node contact including an upper contact having a first width, and a lower contact having a second width that is greater than the first width at a lower portion of the upper contact, a bit line electrically connected to the second impurity implantation region and configured to cross the substrate, a bit line node contact between the bit line and the second impurity implantation region, and a spacer between the storage node contact and the bit line and between the storage node contact and the bit line node contact.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a semiconductor substrate, a bit line electrically connected to the first impurity region, a storage node contact electrically connected to the second impurity region, an air gap between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, a buried dielectric pattern on a sidewall of the landing pad and on the air gap, and a spacer capping pattern between the buried dielectric pattern and the air gap.

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.