Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

Abstract: A smart storage device is provided. The smart storage device includes a smart interface connected to a host device. An accelerator circuit is connected to the smart interface through a data bus conforming to a CXL.cache protocol and a CXL.mem protocol. The accelerator circuit is configured to perform acceleration computation in response to a computation command of the host device. A storage controller is connected to the smart interface through a data bus conforming to a CXL.io protocol. The storage controller is configured to control a data access operation for a storage device in response to a data access command of the host device. The accelerator circuit is directly accessible to the storage device through an internal bus connected directly to the storage controller.

Abstract: A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.

Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

Abstract: A memory module includes a device controller that communicates with a host device based on a first interface including a first clock signal, a first data signal, and a first data strobe signal and operates in one of a first operation mode or a second operation mode depending on an operation mode control value from the host device, and a memory device that communicates with the device controller based on a second interface including a second data signal and a second data strobe signal. The device controller includes a logic circuit that transmits a predetermined training result value to the host device depending on a training control value from the host device, when a training is performed on a third interface being a virtual interface recognized by the host device in the first operation mode.

Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.

Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.

Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command. Status information can be provided at the memory module indicating readiness of the memory module for receipt of an operation command associated with the active command and the associated row address.

Abstract: Provided are a memory device and a memory system including the same. The memory device may include a first memory rank including at least one first memory chip, a memory controller configured to provide a command to the first memory rank, at least one data buffer configured to buffer data input to the at least one first memory chip or being output from the at least one first memory chip, and a second memory rank connected to the first memory rank and comprising at least one second memory chip. The first memory rank may provide training data and a data strobe signal to the second memory rank based on a data training command from the memory controller without the training data and the data strobe signal passing through the data buffer. The second memory rank may determine a delay of the data strobe signal based on the training data being detected by the second memory rank.

Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stored in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the second channel.

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.

Abstract: A method of operating a memory module can include receiving, at the memory module, an active command and an associated row address that indicates that the active command is directed to a volatile memory device included in the memory module or to a non-volatile memory device included in the memory module. The volatile memory device or the non-volatile memory device can be activated based on the associated row address in response to the active command.

Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stared in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the first channel.

Abstract: A nonvolatile memory system includes first and second nonvolatile memory devices and a memory controller configured to control the first and second nonvolatile memory devices through one channel. During a program operation, the memory controller transmits first signals, for setting first page data up in the first nonvolatile memory device, to the first nonvolatile memory device through the channel. While the first nonvolatile memory device sets up the first page data in response to the first signals, the memory controller transmits second signals, for setting second page data up in the second nonvolatile memory device, to the second nonvolatile memory device.