Abstract: A modified conjugated diene-based polymer having high linearity and improved compounding properties is provided. The modified conjugated diene-based polymer includes phosphor, sulfur and chlorine in specific amount ranges, and the degree of branching is controlled, and accordingly, if applied to a rubber composition, tensile strength and viscoelasticity may be excellent, and processability may be markedly improved.

Abstract: An example electronic device includes a display, a communication circuit, a memory, and at least one processor configured to, based on a signal for requesting transmission of identification information including a call word for using first mode of an artificial intelligence assistant function of the electronic device being received, from another electronic device, through the communication circuit using first communication method, control the display to display a user interface for requesting user confirmation for transmission of the identification information; control the communication circuit to transmit the identification information to the another electronic device as a result of user confirmation through the user interface; and receive information for using a second communication method from the another electronic device.

Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Abstract: A method of forming a semiconductor device, includes: forming a design pattern on a substrate, wherein the design pattern protrudes from the substrate; forming a filling layer on the substrate, wherein the filling layer at least partially covers the design pattern; forming a polishing resistance pattern adjacent to the design pattern in the filling layer using a laser irradiation process and/or an ion implantation process; and removing the filling layer using a chemical mechanical polishing (CMP) process to expose the design pattern.

Abstract: A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank.

Abstract: A test board unit may include a test board, a thermal tank and a heat-dissipating plate. The test board may be configured to provide a semiconductor chip with a test current. The thermal tank may be configured to dissipate heat generated in the semiconductor chip. The heat-dissipating plate may be coupled between the test board and the thermal tank and may be configured to transfer the heat from the semiconductor chip to the thermal tank.

Abstract: The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof.

Abstract: The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof.

Abstract: Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.

Abstract: Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

Abstract: Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: The present invention relates to a plasma polymerized thin film having high hardness and a low dielectric constant and a manufacturing method thereof, and in particular, relates to a plasma polymerized thin film having high hardness and a low dielectric constant for use in semiconductor devices, which has improved mechanical strength properties such as hardness and elastic modulus while having a low dielectric constant, and a manufacturing method thereof.

Abstract: Disclosed is a solid state drive tester which divides the functions of generating and comparing test pattern data and Frame Information Structure (FIS) data with each other into each other to implement the functions as separate logics, so that entire test time is decreased by reducing load of a processor. The solid state drive tester includes a host terminal for receiving a test condition for testing a storage from a user, and a test control unit creating a test pattern corresponding to the test condition, and adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, wherein the test control unit is divided into a control module for controlling the test of the storage and a test execution module for practically executing the test in hardware to test a plurality of storages in real time.

Abstract: Disclosed is an error generating apparatus of a solid state drive tester. The error processing operation of the storage is tested by inserting errors into a specific instruction to be transmitted to the storage, and detecting the results of the error processing operation of the storage when testing the storage. The error generating apparatus includes a host terminal for receiving a test condition for a test of a storage from a user, and a test control unit for generating a test pattern according to the test condition or generating a test pattern randomly, generating error data used to test an error characteristic of the storage, and testing the storage based on the test pattern and a normal instruction or an error instruction which is formed by inserting the error data into the normal instruction.

Abstract: Disclosed is a solid state drive tester which reduces the size of the tester and easily changes a function without changing hardware (H/W) by implementing a plurality of devices for testing an SSD as one chip using a Field Programmable Gate Array (FPGA). The solid state drive tester includes: a host terminal receiving a test condition for testing a storage from a user; and a test control unit generating a test pattern corresponding to the test condition, adaptively selecting an interface according to an interface type of the storage to be tested to test the storage using the test pattern, and storing fail data generated during the test in an internal memory. The test control unit is implemented by an FPGA to reduce the size of the tester and easily change a function without hardware.

Abstract: Disclosed is a storage interface apparatus for a solid state drive (SSD) tester which allows a plurality of interfaces to share a single protocol in parts where the protocol is commonly used in a multiple interface for interfacing a storage. The storage interface apparatus for the solid state driver tester includes: a host terminal for receiving a test condition for testing a storage from a user; and a test control unit for generating a test pattern corresponding to the test condition to test the storage. The test control unit includes a storage interface unit for interfacing the storage, and the storage interface unit includes a plurality of interfaces that share a protocol in parts where the protocol is commonly used.

Abstract: The present invention provides a method of manufacturing Ni-doped TiO2 nanotube-shaped powder and a method of manufacturing a sheet film to be inserted into a high-pressure hydrogen tank for a fuel cell vehicle by mixing the Ni-doped TiO2 nanotube-shaped powder with a binder and compressing the mixture. The method of manufacturing Ni-doped TiO2 nanotube-shaped powder includes: forming Ni-doped TiO2 nanotube-shaped powder using Ni-doped TiO2 powder as a starting material; and drying the Ni-doped TiO2 nanotube-shaped powder in the temperature range of 60 to 200° C. for 2 to 24 hours.

Abstract: The present invention provides a method of manufacturing Ni-doped TiO2 nanotube-shaped powder and a method of manufacturing a sheet film to be inserted into a high-pressure hydrogen tank for a fuel cell vehicle by mixing the Ni-doped TiO2 nanotube-shaped powder with a binder and compressing the mixture. The method of manufacturing Ni-doped TiO2 nanotube-shaped powder includes: forming Ni-doped TiO2 nanotube-shaped powder using Ni-doped TiO2 powder as a starting material; and drying the Ni-doped TiO2 nanotube-shaped powder in the temperature range of 60 to 200° C. for 2 to 24 hours.

Abstract: A semiconductor memory device and a failed cell address programming circuit usable therein.