Patents by Inventor Hyok-ki Kwon
Hyok-ki Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140043896Abstract: A method of preventing program-disturbances for a non-volatile semiconductor memory device having a plurality of memory cells of which each includes a selection transistor and a memory transistor coupled in series between a bit-line and a common source-line is provided. First non-selected memory cells that share a first selection-line with a selected memory cell, and second non-selected memory cells that do not share the first selection-line with the selected memory cell are determined when the selected memory cell is selected to be programmed among the memory cells. A negative voltage is applied to second selection-lines that are coupled to the second non-selected memory cells when the selected memory cell is programmed by applying a positive voltage to the first selection-line that is coupled to the selected memory cell.Type: ApplicationFiled: July 11, 2013Publication date: February 13, 2014Inventors: Weon-Ho Park, Hyok-Ki Kwon, Min-Sup Kim, Min-Su Kim, Byoung-Ho Kim, Eui-Yeol Kim, Sang-Hoon Park, Ji-Hoon Park, Min-Jee Sung, Hyo-Soung Sim, Chang-Min Jeon, Hee-Seog Jeon
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Patent number: 7973314Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.Type: GrantFiled: May 8, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Tae Kim, Yong-Suk Choi, Hyok-Ki Kwon
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Patent number: 7855410Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.Type: GrantFiled: July 7, 2008Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Jeong-Uk Han, Yong-Suk Choi, Hyok-Ki Kwon, Bae-Seong Kwon
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Patent number: 7820516Abstract: Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.Type: GrantFiled: May 15, 2007Date of Patent: October 26, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Jin Yang, Hyok-ki Kwon, Yong-Seok Choi, Jeong-Uk Han
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Patent number: 7642593Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.Type: GrantFiled: January 26, 2007Date of Patent: January 5, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Suk Choi, Jeong-Uk Han, Hee-Seog Jeon, Yong-Tae Kim, Seung-Jin Yang, Hyok-Ki Kwon
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Publication number: 20090278192Abstract: A semiconductor device includes a tunnel insulation layer pattern, a charge trapping layer pattern, a blocking layer pattern and a gate structure. The tunnel insulation layer pattern is formed on a substrate. The charge trapping layer pattern is formed on the tunnel insulation layer pattern. The blocking layer pattern is formed on the substrate and extends up onto and covers the charge trapping layer pattern. The gate surrounds an upper portion of the charge trapping layer pattern so as to face towards and upper surface and opposite side surfaces of the charge trapping layer pattern.Type: ApplicationFiled: May 1, 2009Publication date: November 12, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Suk CHOI, Jeong-Uk HAN, Yong-Tae KIM, Seung-Jin YANG, Hyok-Ki KWON
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Patent number: 7602004Abstract: A semiconductor device includes a first transistor and a second transistor formed on a substrate. Each of the first transistor and the second transistor has a first source region, first drain region of a first conductivity type and a gate. The first transistor is an off-transistor and includes a second source/drain region of the first conductivity type which surrounds at least a portion of the first source/drain region in the first transistor.Type: GrantFiled: October 24, 2006Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Seog Jeon, Jeong-Uk Han, Hyok-Ki Kwon
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Patent number: 7602008Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: GrantFiled: December 14, 2007Date of Patent: October 13, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Taeg Kang, Hyok-Ki Kwon, Bo Young Seo, Seung Beom Yoon, Hee Seog Jeon, Yong-Suk Choi, Jeong-Uk Han
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Patent number: 7554150Abstract: A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.Type: GrantFiled: May 17, 2007Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., LtdInventors: Hong-Kook Min, Yong-Suk Choi, Hyok-Ki Kwon
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Patent number: 7553725Abstract: A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.Type: GrantFiled: July 18, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-Seog Jeon, Jeong-Uk Han, Chang-Hun Lee, Sung-Taeg Kang, Bo-Young Seo, Hyok-Ki Kwon
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Patent number: 7531410Abstract: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.Type: GrantFiled: December 29, 2006Date of Patent: May 12, 2009Assignee: Samsung Electronic Co., Ltd.Inventors: Yong-Suk Choi, Jeong-Uk Han, Hee-Seog Jeon, Seung-Jin Yang, Hyok-Ki Kwon
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Publication number: 20090008696Abstract: According to one embodiment, a semiconductor memory device can be generally characterized as including a gate insulating layer on a semiconductor substrate, a floating gate on the gate insulating layer and a word line disposed on one side of the floating gate. A first side of the floating gate facing the word line may include a projecting portion projecting toward the word line. A tip of the projecting portion may include a corner that extends substantially perpendicularly with respect to a top surface of the semiconductor substrate.Type: ApplicationFiled: July 7, 2008Publication date: January 8, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin YANG, Jeong-Uk HAN, Yong-Suk CHOI, Hyok-Ki KWON, Bae-Seong KWON
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Publication number: 20080283873Abstract: A semiconductor device has a first semiconductor layer including a first circuit, a second semiconductor layer disposed on the first semiconductor layer and having a second circuit, and a via extending through portions of the first and second semiconductor layers and by which the first and second circuits are electrically connected. One of the circuits is a logic circuit and the other of the circuits is a memory circuit. The semiconductor device is manufactured by fabricating transistors of the logic and memory circuits on respective substrates, stacking the substrates, and electrically connecting the logic and memory circuits with a via.Type: ApplicationFiled: May 8, 2008Publication date: November 20, 2008Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seung-Jin YANG, Jeong-Uk HAN, Yong-Tae KIM, Yong-Suk CHOI, Hyok-Ki KWON
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Publication number: 20080093647Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: ApplicationFiled: December 14, 2007Publication date: April 24, 2008Inventors: Sung-Taeg KANG, Hyok-Ki Kwon, Bo Seo, Seung Yoon, Hee Jeon, Yong-Suk Choi, Jeong-Uk Han
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Patent number: 7338861Abstract: A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench.Type: GrantFiled: April 20, 2005Date of Patent: March 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-chul Kim, Young-cheon Jeong, Hyok-ki Kwon
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Publication number: 20080042186Abstract: A non-volatile memory device includes isolation layers, a cell trench, a floating gate, a common source region and a word line. The isolation layers define an active region of a substrate. The cell trench is formed in the active region. The cell trench extends in a first direction. The floating gate is formed on the active region and in the cell trench. The common source region is formed on the active region adjacent a second side face of the floating gate and extends in a second direction substantially perpendicular to the first direction. The word line is formed on the active region, which is adjacent to a first side face of the floating gate opposite to the second side face, and the isolation layers and in the cell trench. The word line extends in the second direction.Type: ApplicationFiled: May 17, 2007Publication date: February 21, 2008Inventors: Hong-Kook Min, Yong-Suk Choi, Hyok-Ki Kwon
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Patent number: 7320913Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: GrantFiled: March 3, 2006Date of Patent: January 22, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Taeg Kang, Hyok-Ki Kwon, Bo Young Seo, Seung Beom Yoon, Hee Seog Jeon, Yong-Suk Choi, Jeong-Uk Han
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Publication number: 20080002475Abstract: Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.Type: ApplicationFiled: May 15, 2007Publication date: January 3, 2008Inventors: Seung-Jin Yang, Hyok-ki Kwon, Yong-Seok Choi, Jeong-Uk Han
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Patent number: 7315057Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.Type: GrantFiled: March 3, 2006Date of Patent: January 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Seog Jeon, Sung-Taeg Kang, Hyok-Ki Kwon, Yong Tae Kim, BoYoung Seo, Seung Beom Yoon, Jeong-Uk Han
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Publication number: 20070278531Abstract: A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.Type: ApplicationFiled: December 29, 2006Publication date: December 6, 2007Inventors: Yong-Suk Choi, Jeong-Uk Han, Hee-Seog Jeon, Seung-Jin Yang, Hyok-Ki Kwon