Abstract: A nonvolatile semiconductor memory with a unit cell structure suitable for high speed operation and a low power supply voltage. The nonvolatile semiconductor memory includes a switching circuit including block select transistors connected by its respective terminal to a corresponding bit line. This switching circuit transmits a signal only when a string to which the switching circuit corresponds is selected. A second active region having a different impurity concentration from a first active region constituting source and drain regions of memory transistors is formed at a substrate contact portion of a bit line contact portion where the memory string and bit line are connected. The impurity concentration of the second active region is lower than that of the first active region.

Abstract: A nonvolatile memory device containing sub memory arrays and distinct associated peripheral sub array circuits containing error checking and correction circuits that are similarly positioned according to the sub array. The memory device is configured so that a single mask change allows the device to be manufactured as a normal mode device or a page mode device.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A data output control circuit of a semiconductor memory device. The data output control circuit comprises an input signal detector for detecting a desired signal, a controller for selecting one of a plurality of data output buffers and a data output controller for driving the selected data output buffer. A signal for driving and controlling the data output buffer is enabled after the data of a given memory cell is supplied to an input terminal of the data output buffer so that any unnecessary transition operation of data can be eliminated to reduce the current dissipation of a semiconductor memory chip and to prevent the deterioration of data access time for the purpose of improving the yield of the semiconductor memory chip.

Abstract: A semiconductor memory device having a NAND-type memory cell structure for preventing the occurrence of an electrical bridge resulting from impurity particles generated during a manufacturing process. The space between the word-line whereto a Vcc voltage is applied and the string selection line whereto a Vss voltage is applied and a space between the string selection line of the string selection transistor and the word-line of the cell transistor adjacent to the string selection transistor, are wider than that between the word-lines so as to prevent early stand-by current failure caused by the special stand-by conditions of a NAND-type memory cell. Therefore, the occurrence of a polysilicon bridge between the word-line and the string selection line due to impurity particles generated during the manufacturing process is prevented. As a result, a defectively manufactured chip can be resurrected by the data correction means provided within the memory device.

Abstract: A semiconductor memory device which is comprised of a plurality m of electrically isolated data memory sub-arrays for storing data bits and a plurality k of electrically isolated parity memory sub-arrays for storing parity bits, wherein each of the data and parity memory sub-arrays includes a plurality of memory cells arranged in a matrix of rows and columns, with the memory cells in each row connected to a common word line and the memory cells in each column connected to a common bit line. Row address decoders function to activate a selected word line in each of the memory sub-arrays, and column address decoders, in combination with column selection circuitry, function to couple a selected bit line in each of the memory sub-arrays to a plurality m of sense amplifiers, which function to sense the voltage level of respective ones of the selected bit lines, and produce output data and parity bits representative of these sensed voltage levels.

Abstract: An output buffer circuit for a byte wide memory is disclosed, including a circuit for delaying the falling or rising time of the gate voltage of a pull-up transistor of an output driver, located between a p-channel transistor and an n-channel transistor of the pull-up inverter; and a circuit for delaying the rising time of the gate voltage of a pull-down transistor of the output driver, located between a p-channel transistor and an n-channel transistor of the pull-down inverter. The disclosed delay circuits may include a depletion transistor having a gate and a source connected to each other. Through the provision of such delay mechanisms, the noise generations in both the power lines and the ground lines are reduced.