Abstract: A three dimensional image display device includes a display panel in which at least one of two consecutive left eye images and two consecutive right eye images are inputted, where the two consecutive left eye images are substantially the same as each other, and the two consecutive right eye images are substantially the same as each other, and where gate scanning directions of the two consecutive left eye images are opposite to each other, and gate scanning directions of the two consecutive right eye images are opposite to each other.

Abstract: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.

Abstract: A three dimensional image display device includes a display panel in which at least one of two consecutive left eye images and two consecutive right eye images are inputted, where the two consecutive left eye images are substantially the same as each other, and the two consecutive right eye images are substantially the same as each other, and where gate scanning directions of the two consecutive left eye images are opposite to each other, and gate scanning directions of the two consecutive right eye images are opposite to each other.

Abstract: A display device includes gate lines; data lines; charge control lines each including a charge control voltage input pad; first and second thin film transistors (TFTs) each including control and input electrodes connected to the gate and data lines, respectively; a first liquid crystal capacitor connected to an output electrode of the first TFT; a second liquid crystal capacitor connected to an output electrode of the second TFT; a charge control TFT including a control electrode and an input electrode connected to one of the charge control lines and the second pixel electrode, respectively; and a charge-down capacitor connected to an output electrode of the charge control TFT. A duration time of a turn-on voltage pulse applied to the charge control TFT is different from a duration time of a turn-on voltage pulse applied to the first TFT transistor or the second TFT.