Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed.

Abstract: A first surface of a debonder defines a recess that holds an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface. The second surface includes suction openings that deliver suction to the recess. A third surface of the debonder substantially connects the first and the second surfaces and includes an opening dimensioned to limit a pressure differential between the recess and outside the recess during application of the suction.

Abstract: A first surface of a debonder defines a recess to hold an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The carrier plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the carrier plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface, where the second surface includes suction openings that deliver a suction force to the recess, and a portion of the second surface is in contact with a heat source.

Abstract: A first surface of a debonder defines a recess to hold an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The carrier plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the carrier plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface, where the second surface includes suction openings that deliver a suction force to the recess, and a portion of the second surface is in contact with a heat source.

Abstract: A first surface of a debonder defines a recess that holds an assembly that includes a wafer bonded to a carrier plate having a first diameter that is larger than a second diameter of the wafer. The plate includes a peripheral area not covered by the wafer, and when the wafer of the assembly is placed within the recess, a portion of the peripheral area of the plate engages a portion of the first surface. A second surface of the debonder is disposed in the recess and is separated from the first surface. The second surface includes suction openings that deliver suction to the recess. A third surface of the debonder substantially connects the first and the second surfaces and includes an opening dimensioned to limit a pressure differential between the recess and outside the recess during application of the suction.

Abstract: Disclosed are systems, devices and methodologies for debonding wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be debonded from the carrier plate. Such a debonding process can be achieved by applying a suction force to the wafer-carrier plate assembly. Various debonding systems, devices and methodologies, and related features, are disclosed.

Abstract: Disclosed are systems, devices and methodologies for debonding wafers from carrier plates. In certain wafer processing operations, it is desirable to temporarily mount a wafer on a carrier plate for support and ease of handling. Such a mounting can be achieved by bonding the wafer and the carrier plate with an adhesive. Once such operations are completed, the wafer needs to be debonded from the carrier plate. Such a debonding process can be achieved by applying a suction force to the wafer-carrier plate assembly. Various debonding systems, devices and methodologies, and related features, are disclosed.

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract: A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate a control signal corresponding to the range of the level of the external power voltage responsive to the voltage detecting signal. As a result, the semiconductor memory device can perform an operation for satisfying an access time characteristic according to a specification responsive to the control signal.

Abstract: A semiconductor memory device includes a plurality of output buffer units connected to a plurality of terminals. Each of the output buffer units includes a first high speed data output (HSDO) buffer adapted to buffer even-numbered data of a corresponding data row among a plurality of data rows and to output the even-numbered data to a corresponding terminal among the plurality of terminals, a second HSDO buffer adapted to buffer odd-numbered data of the corresponding data row and to output the odd-numbered data to the corresponding terminal, and a buffer selector adapted to select and activate the first HSDO buffer and/or the second HSDO buffer in response to a corresponding control signal out of at least one control signal during a HSDO test.

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input.

Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.

Abstract: A semiconductor memory device and a control signal generating method thereof. The semiconductor memory device may include a voltage range detector configured to generate a voltage detecting signal corresponding to a range of a level of an external power voltage. A control signal generating portion may be used to generate a control signal corresponding to the range of the level of the external power voltage responsive to the voltage detecting signal. As a result, the semiconductor memory device can perform an operation for satisfying an access time characteristic according to a specification responsive to the control signal.

Abstract: Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write or read operation, as the frequency at which the semiconductor device operates increases. The mode register setting methods and apparatuses may be applied, for example, to DDR-type semiconductor devices. If a chip selection signal /CS maintains a logic low level for at least a first amount of time, a semiconductor device may initiate a clock-independent mode register setting operation. In the clock-independent mode register setting operation, a mode register set (MRS) command and an MRS code bit may be sampled when the logic level of a data strobe signal applied to the semiconductor device transitions from a logic low level to a logic high level.

Abstract: Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate.

Abstract: A semiconductor memory device and a method for testing the same are capable of performing a low-frequency test operation even when a high-frequency external clock signal is input.