Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Abstract: In one embodiment, a solid state storage drive comprises a plurality of flash memory devices communicatively coupled to a bus and a channel controller communicatively coupled to the bus, the channel controller comprising an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate presently assigned for communications over the bus, and a channel execution unit configured to determine when to place a second command in a command execution queue based at least in part on the aggregate execution time duration. In one embodiment, the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate and a data payload quantity associated with at least one command in the sequence of commands.

Abstract: In one embodiment, a solid state storage drive comprises a plurality of flash memory devices communicatively coupled to a bus and a channel controller communicatively coupled to the bus, the channel controller comprising an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate presently assigned for communications over the bus, and a channel execution unit configured to determine when to place a second command in a command execution queue based at least in part on the aggregate execution time duration. In one embodiment, the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate and a data payload quantity associated with at least one command in the sequence of commands.

Abstract: A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Abstract: An apparatus and method for managing a dynamic random access memory (DRAM) buffer are disclosed. The DRAM buffer managing apparatus and method may generate an error correction code (ECC) for data to be written in a DRAM buffer, and may write the data and the ECC in the DRAM buffer.