Abstract: A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip.

Abstract: The invention relates to an LED package and proposes a method of fabricating an LED package including steps of providing a package substrate having a mounting area of an LED and a metal pattern to be connected with the LED, and plasma-treating the package substrate to reform at least a predetermined surface area of the package substrate where a resin-molded part will be formed. The method also includes mounting the LED on the mounting area on the substrate package and electrically connecting the LED with the metal pattern, and forming the resin-molded part in the mounting area of the LED to seal the LED package.

Abstract: A method for manufacturing a multilayer ceramic capacitor, in which internal electrodes printed on each of a plurality of dielectric sheets have reduced thicknesses using an absorption member, thereby allowing the multilayer ceramic capacitor to have a high capacity and be minimized. The method includes printing the internal electrodes on each of the dielectric sheets, and stacking the dielectric sheets, wherein the internal electrodes formed on each of the dielectric sheets have a reduced thickness by causing an absorptive member to contact the surface of each of the dielectric sheets provided with the internal electrodes and then separating the absorptive member from the surface so that portions of the internal electrodes having a designated thickness are eliminated, and the dielectric sheets provided with the internal electrodes having the reduced thickness are stacked to form a chip element.

Abstract: A multilayer chip capacitor, and a method for manufacturing the same are provided. The capacitor includes a capacitor body having a plurality of dielectric layers stacked therein, a plurality of first and second internal electrodes formed on the dielectric layers, each of the internal electrodes including a main electrode portion and a lead portion, chip-protecting side members formed on both sides of the capacitor body to contact both sides of the first and second internal electrodes, and a pair of external electrodes formed on the outer surface of the capacitor body. The width of the main electrode portion is the same as that of the dielectric layers, and the width of the lead portion is smaller than that of the dielectric layers.

Abstract: Disclosed herein is a method of manufacturing a multilayered ceramic capacitor by a spin coating process, and a multilayered ceramic capacitor obtained by the above method. The method of the current invention provides a plurality of dielectric layers formed by spin coating, in which the process of coating the dielectric layer and the process of printing the inner electrode can be provided as a single process. Therefore, the thickness of the dielectric layer is easily controlled while the dielectric layer is formed to be thin. Further, since the dielectric layers and the inner electrodes are formed successively, the processes of separating and layering the dielectric layers, and the process of compressing the ceramic multilayered body can be omitted. Thereby, the ceramic multilayered body need not be compressed, and thus, a pillowing phenomenon does not occur in the multilayered ceramic capacitor.

Abstract: A TAB tape for a semiconductor package is provided. The TAB tape provides number of test pad configuration for reducing the area of the test pad area on a TAB tape to increases the number of packages that may be prepared from a length of TAB tape. The TAB tape comprises a base film having a chip mounting area for mounting at least one semiconductor device and a wiring pattern formed on the base film with test pads formed at the ends of the output terminal patterns. A predetermined number of the test pads are arranged in rows form a group wherein the number of rows is less than the number of test pads in the group. Groups of the test pads are consecutively arranged across the TAB tape to provide the number of test pads necessary for testing the semiconductor device(s).

Abstract: The present invention relates to a high frequency composite component used in a front end section for processing a high frequency signal between a transceiving section and an antenna in a high frequency circuit of a mobile communication device.

Abstract: A TAB tape for a semiconductor package is provided. The TAB tape provides number of test pad configuration for reducing the area of the test pad area on a TAB tape to increases the number of packages that may be prepared from a length of TAB tape. The TAB tape comprises a base film having a chip mounting area for mounting at least one semiconductor device and a wiring pattern formed on the base film with test pads formed at the ends of the output terminal patterns. A predetermined number of the test pads are arranged in rows form a group wherein the number of rows is less than the number of test pads in the group. Groups of the test pads are consecutively arranged across the TAB tape to provide the number of test pads necessary for testing the semiconductor device(s).

Abstract: A chip on film (COF) package comprising a test pad for testing the electrical function of a semiconductor chip and a method for manufacturing same are provided. The COF package comprises a semiconductor chip mounted on a base film, a signal-input portion for receiving data and control signals and transmitting the data and control signals to the semiconductor chip, a plurality of passive elements connected to terminals of the semiconductor chip, and a plurality of test pads for testing one or more terminals of the semiconductor chip that are not connected to the signal-input portion. The test pads of the COF package are capable of testing a plurality of internal terminals which are integrated into one terminal and do not connected to the signal-input portion, thereby easily testing the electrical function of the chip.

Abstract: The invention relates to a product to permit separation of cells in the domain of immunopurification and consisting of a finely divided carrier of a density lower than that of the medium from which such cells must be extracted, such carrier being covered with macromolecules capable of being specifically fixed to the cells to be extracted to which a priviliged orientation was given to enable fixation of such macromolecules.