Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.

Abstract: A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.

Abstract: A fuse circuit includes a program unit and a sensing unit. The program unit is programmed in response to a program signal and outputs a program output signal in response to a sensing enable signal. The sensing unit outputs a sensing output signal based on the program output signal and the sensing output signal indicates whether the program unit is programmed or not. The program unit includes an anti-fuse cell, a selection transistor, a program transistor and a sensing transistor. The anti-fuse cell includes at least two anti-fuse elements which are connected in parallel and are respectively broken down at different levels of a program voltage.

Abstract: A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.

Abstract: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.

Abstract: A recessed channel transistor, a semiconductor device including a transistor and methods of manufacturing the same are provided, the recessed channel transistor includes a gate structure, a second impurity region and a first impurity region. The gate structure may be formed on a substrate and filling a recess. The first impurity region, including first impurities, may be formed at a first upper portion of the substrate adjacent to the gate structure. The second impurity region, including second impurities, may be formed at a second upper portion of the substrate contacting the gate structure. The first impurity region may surround the second impurity region. The first impurities have a conductive type different from that of the second impurities.

Abstract: In a method of manufacturing a transistor, a gate structure is formed on a substrate. First impurities are implanted into the substrate to form an impurity region at an upper portion of the substrate adjacent to the gate structure. An epitaxial layer is formed on the impurity region. An insulation layer having an opening partially exposing the epitaxial layer is formed on the substrate. Second impurities are implanted into a portion of the epitaxial layer exposed by the opening.

Abstract: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.

Abstract: A wiring structure in a semiconductor device includes a first insulation layer formed on a substrate having first and second contact regions, and first and second pads extending through the first insulation layer and contacting the first and the second contact regions. The first and the second pads are higher than the first insulation layer. A blocking layer pattern is formed on the first insulation layer between the first and the second pads, the blocking layer pattern being higher than the first and the second pads. A second insulation layer is formed on the blocking layer pattern and the first and the second pads. A bit line structure is formed on the second insulation layer, the bit line structure electrically contacting the second pad. A third insulation layer is formed on the second insulation layer and the bit line structure. A plug extends through the second and the third insulation layers and contacts the first pad.

Abstract: A semiconductor device includes an active region defined in a substrate, the active region having a trench extending below a surface of the substrate; an impurity region provided along a bottom surface and a lower sidewall of the trench, wherein an upper portion of the impurity region is spaced apart from the surface of the substrate and an upper portion of the trench; a gate insulating layer provided along an inner surface of the trench; and a gate electrode provided in the trench.

Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.

Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.

Abstract: A semiconductor device such as a Static Random Access Memory (SRAM) cell includes an access transistor. A drain of the access transistor includes a first N-type impurity and a second N-type impurity. The diffusion coefficient of the first N-type impurity is smaller than the diffusion coefficient of the second N-type impurity. By providing a drain as described above, hot carrier effects within the access transistor may be minimized.

Abstract: A method of forming an SRAM cell, having two transfer transistors, two driver transistors, and two load devices which are connected with one another in the form of a flip-flop is provided. In particular, after defining an active region and an inactive region on a silicon substrate, a gate electrode conductive pattern of the transistors is formed on the silicon substrate having the active region and the inactive region formed therein along a channel width direction (X-axis direction). Then, after forming a pocket ion implantation region under the conductive pattern, by performing a photolithography process on the conductive pattern along a channel length direction (Y-axis direction), the gate electrodes of the transistors are formed. Even though the gate electrodes are misaligned, impurities for pocket ion implantation are not injected into the gate extension along the channel width direction.

Abstract: A semiconductor device with improved soft error rate immunity and latch-up immunity and a method of forming the same. The device includes first wells of first conductivity type and second well of second conductivity type formed in the semiconductor substrate of first conductivity type. First conductivity type MOSFETs including source/drain of first conductivity type are formed in the second well, and second conductivity type MOSFETs including source/drain of second conductivity type in the first well. A third well of second conductivity type is formed at a region under the first wells and the drain of the second conductivity type MOSFETs. The first well is connected to the semiconductor substrate between the first well and the third well.

Abstract: Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures.

Abstract: An electrostatic discharge protective circuit including a semiconductor substrate, an input/output pad formed on the semiconductor substrate, a PMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, a first n+ diffusion layer formed in the semiconductor substrate and separated from the drain of the PMOS transistor at a predetermined interval while being connected to a Vcc terminal, a deep n+ diffusion layer formed between the drain of the PMOS transistor and the first n+ diffusion layer, an NMOS transistor formed on the semiconductor substrate and having a drain connected to the input/output pad, and second n+ diffusion layers formed around the NMOS transistor in the semiconductor substrate and connected to a Vss terminal.

Abstract: Disclosed are a method for forming a structure of wires for a semiconductor device in which pads are formed for contact in cell regions as well as core regions and periphery regions where cell aspect ratios are very high, and a structure of wires so formed. The semiconductor device includes a semiconductor substrate arranged into cell regions and periphery and/or core regions, the periphery and/or core regions having a well formed in the semiconductor substrate, the semiconductor substrate being arranged into active regions and field regions, the semiconductor device also having field insulating layers in the field regions, plural gate structures on portions of the semiconductor substrate in the active regions, and impurity regions in the semiconductor substrate between the gate structures.

Abstract: The ESD protection circuit disclosed, including: a second conductivity of well formed in a predetermined portion of a first conductivity of semiconductor substrate; a first conductivity of first impurity region and second conductivity of second impurity region, formed in the second conductivity of well; a first gate electrode formed on the semiconductor substrate, and second gate electrode formed on the first gate electrode, the first gate electrode being isolated from the semiconductor substrate; second conductivity of third and fourth impurity regions, formed in a portion of the semiconductor substrate, the portion being placed on both sides of the first and second gate electrodes; and a second conductivity of fifth impurity region formed on the semiconductor substrate, the fourth and fifth impurity regions having an isolation layer therebetween.