Patents by Inventor Hyuck-Jun Cho

Hyuck-Jun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Smart card device, system including the same and method of operating smart card system
    Patent number: 10565405
    Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuck-Jun Cho, Donald Na, Seung-Hwan Baek, Jae-Keun Oh, Kee-Moon Chun
  • SMART CARD DEVICE, SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING SMART CARD SYSTEM
    Publication number: 20170169256
    Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 15, 2017
    Inventors: Hyuck-Jun CHO, Donald NA, Seung-Hwan BAEK, Jae-Keun OH, Kee-Moon CHUN
  • Method of operating smart card and method of operating smart card system including the same
    Patent number: 9589221
    Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: March 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyuck-Jun Cho, Donald Na, Seung-Hwan Baek, Jae-Keun Oh, Kee-Moon Chun
  • METHOD OF OPERATING SMART CARD AND METHOD OF OPERATING SMART CARD SYSTEM INCLUDING THE SAME
    Publication number: 20160078337
    Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.
    Type: Application
    Filed: August 6, 2015
    Publication date: March 17, 2016
    Inventors: Hyuck-Jun Cho, Donald Na, Seung-Hwan Baek, Jae-Keun Oh, Kee-Moon Chun
  • Semiconductor integrated circuit and testing method thereof
    Patent number: 8332662
    Abstract: A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: December 11, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Kwon Kim, Byeong-Hoon Lee, Ki-Hong Kim, Hyuck-Jun Cho
  • SEMICONDUCTOR INTEGRATED CIRCUIT AND TESTING METHOD THEREOF
    Publication number: 20090095955
    Abstract: A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Inventors: Sun-Kwon Kim, Byeong-Hoon Lee, Ki-Hong Kim, Hyuck-Jun Cho