Patents by Inventor Hyuck-Sang Yim
Hyuck-Sang Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10903419Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.Type: GrantFiled: June 23, 2020Date of Patent: January 26, 2021Assignee: SK hynix Inc.Inventors: Hyuck Sang Yim, Myung Sun Song
-
Patent number: 10861540Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.Type: GrantFiled: February 18, 2018Date of Patent: December 8, 2020Assignee: SK hynix Inc.Inventor: Hyuck-Sang Yim
-
Publication number: 20200321519Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.Type: ApplicationFiled: June 23, 2020Publication date: October 8, 2020Applicant: SK hynix Inc.Inventors: Hyuck Sang YIM, Myung Sun SONG
-
Patent number: 10727403Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.Type: GrantFiled: December 5, 2018Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventors: Hyuck Sang Yim, Myung Sun Song
-
Patent number: 10699760Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.Type: GrantFiled: November 28, 2018Date of Patent: June 30, 2020Assignee: SK hynix Inc.Inventors: Hyuck Sang Yim, Ki Won Lee, Seoung Ju Chung
-
Publication number: 20190341545Abstract: A resistive memory device may include a plurality of MATs, row control blocks, a plurality of word lines, a plurality of bit lines and memory cells. Each of the row control blocks may be interposed between the MATs. Each of the row control blocks may include a control element. The word lines may be arranged spaced apart from each other by a substantially uniform gap on the MATs. The bit lines may overlap with the word lines. The memory cells may be located between the word lines and the bit lines. Each of the word lines may be electrically connected with the control element of each of the row control blocks via a connection path.Type: ApplicationFiled: December 5, 2018Publication date: November 7, 2019Applicant: SK hynix Inc.Inventors: Hyuck Sang YIM, Myung Sun SONG
-
Publication number: 20190333555Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.Type: ApplicationFiled: November 28, 2018Publication date: October 31, 2019Applicant: SK hynix Inc.Inventors: Hyuck Sang YIM, Ki Won LEE, Seoung Ju CHUNG
-
Patent number: 10403346Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.Type: GrantFiled: February 23, 2018Date of Patent: September 3, 2019Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.Inventors: Katsuyuki Fujita, Hyuck Sang Yim
-
Publication number: 20180182442Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.Type: ApplicationFiled: February 23, 2018Publication date: June 28, 2018Applicants: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.Inventors: Katsuyuki FUJITA, Hyuck Sang YIM
-
Publication number: 20180174651Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.Type: ApplicationFiled: February 18, 2018Publication date: June 21, 2018Inventor: Hyuck-Sang Yim
-
Patent number: 9899080Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.Type: GrantFiled: October 24, 2016Date of Patent: February 20, 2018Assignee: SK hynix Inc.Inventor: Hyuck-Sang Yim
-
Patent number: 9870821Abstract: An electronic device including a semiconductor memory is disclosed. The semiconductor memory includes a read path including a unit storage cell; a reference path including a unit reference cell; read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path in response to a read voltage and a reference voltage, and sensing data stored in the unit storage cell based on the comparison result; a first replica path suitable for modeling the read path; and a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage.Type: GrantFiled: December 31, 2014Date of Patent: January 16, 2018Assignee: SK hynix Inc.Inventor: Hyuck-Sang Yim
-
Publication number: 20170294226Abstract: An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.Type: ApplicationFiled: October 24, 2016Publication date: October 12, 2017Inventor: Hyuck-Sang Yim
-
Patent number: 9741434Abstract: According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive lines each extending from a first end to a second end of the memory cell array in the column direction, a first resistance change element connected between the first and second main global conductive lines inside the memory cell array, a first reference global conductive line extending from the first end to the second end of the memory cell array in the column direction, and a second resistance change element connected to the reference global conductive line outside the memory cell array.Type: GrantFiled: September 4, 2013Date of Patent: August 22, 2017Assignees: SK HYNIX INC., KABUSHIKI KAISHA TOSHIBAInventors: Akira Katayama, Masahiro Takahashi, Tsuneo Inaba, Hyuck Sang Yim, Dong Keun Kim, Byoung Chan Oh, Ji Wang Lee
-
Patent number: 9336871Abstract: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.Type: GrantFiled: July 28, 2015Date of Patent: May 10, 2016Inventors: Masahiro Takahashi, Dong Keun Kim, Hyuck Sang Yim
-
Publication number: 20150340087Abstract: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.Type: ApplicationFiled: July 28, 2015Publication date: November 26, 2015Inventors: Masahiro TAKAHASHI, Dong Keun KIM, Hyuck Sang YIM
-
Publication number: 20150287454Abstract: An electronic device including a semiconductor memory is disclosed. The semiconductor memory includes a read path including a unit storage cell; a reference path including a unit reference cell; read circuit suitable for comparing a read current flowing on the read path with a reference current flowing on the reference path in response to a read voltage and a reference voltage, and sensing data stored in the unit storage cell based on the comparison result; a first replica path suitable for modeling the read path; and a reference voltage generation unit suitable for generating the reference voltage corresponding to a first replica current flowing on the first replica path in response to the read voltage.Type: ApplicationFiled: December 31, 2014Publication date: October 8, 2015Inventor: Hyuck-Sang Yim
-
Patent number: 9153318Abstract: A semiconductor device includes: a write current generator configured to generate a write current corresponding to a write reference voltage in a write mode and to have a negative feedback structure. The semiconductor device may further comprise a variable resistance device configured to have a resistance value that varies with the write current.Type: GrantFiled: July 25, 2013Date of Patent: October 6, 2015Assignee: SK Hynix Inc.Inventor: Hyuck-Sang Yim
-
Patent number: 9123412Abstract: According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.Type: GrantFiled: September 4, 2013Date of Patent: September 1, 2015Inventors: Masahiro Takahashi, Dong Keun Kim, Hyuck Sang Yim
-
Patent number: 9019746Abstract: A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.Type: GrantFiled: March 16, 2013Date of Patent: April 28, 2015Assignee: SK Hynix Inc.Inventors: Hyuck-Sang Yim, Taek Sang Song