Abstract: A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal.

Abstract: A phase change memory apparatus includes a global bit line and an internal power generation circuit. The global bit line is configured to integratedly control a plurality of bit lines. The internal power generation circuit is configured to supply an internal voltage while the global bit line is discharged and configured to control the internal voltage after the global bit line is discharged, when a deep power down mode signal is enabled.

Abstract: A semiconductor memory device prevents a faulty operation of a program operation, and increases the reliability of operation. The semiconductor memory device includes a unit cell including a memory element configured to have a different resistance value in response to data, and a write driver configured to output a program current and voltage for programming the unit cell in response to a test signal.

Abstract: A phase-change memory device includes: a unit cell including a phase-change resistor; a sense amplifier applying a sensing current to the phase-change resistor; and a switching unit operating in a standby mode or a read mode according to a global line signal and controlling passing presence of the sensing current passing through the phase-change resistor according to an active signal in the standby mode.

Abstract: Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data.

Abstract: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.

Abstract: A semiconductor memory device includes a plurality of memory banks each having a plurality of memory cell arrays, a plurality of sense amplification units corresponding to the memory banks, configured to sense data corresponding to a selected memory cell to amplify the sensed data, and a common delay unit configured to delay a plurality of respective bank active signals activated in correspondence with the memory banks by a predetermined time to generate an operation control signal for controlling the sense amplification units.

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A semiconductor memory apparatus includes a bit line coupled to a plurality of memory cells, a discharge controller configured to generate a bit line discharge signal to pre-discharge the bit line before the memory cells are activated, and a bit line discharge block coupled to the bit line and configured to discharge the bit line in response to the bit line discharge signal.

Abstract: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Abstract: A phase change memory device includes a signal generator configured to generate first and second sensing and amplifying enable signals which are sequentially activated during an activation period of a word line selection signal and each of which has a certain activation period length, a resistance sensor configured to sense a resistance value by applying a certain operation current to a phase change memory cell corresponding to the word line selection signal during an activation period of the first sensing and amplifying enable signal and a voltage level amplifier configured to logically determine a voltage level of the resistance sensing signal based on a voltage level of a logic reference signal during an activation period of the second sensing.

Abstract: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A phase-change memory device includes: a unit cell including a phase-change resistor; a sense amplifier applying a sensing current to the phase-change resistor; and a switching unit operating in a standby mode or a read mode according to a global line signal and controlling passing presence of the sensing current passing through the phase-change resistor according to an active signal in the standby mode.

Abstract: A semiconductor memory device includes: a first bank and a second bank; one or more first data input/output pads disposed at one side of the first bank and used in access to data of the first bank; one or more second data input/output pads disposed at one side of the second bank and used in access to data of the second bank; a first cyclic redundancy code (CRC) generation circuit for generating a first CRC using a plurality of data output from the first bank and outputting the generated first CRC through the first data input/output pads; and a second CRC generation circuit for generating a second CRC using a plurality of data output from the second bank and outputting the generated second CRC through the second data input/output pads.

Abstract: A nonvolatile memory device includes a plurality of programming current driving units configured to supply memory cells with a programming current corresponding to a write data, a common programming current controlling unit configured to generate a common control voltage for controlling the programming current and a switching unit configured to transfer the common control voltage to the programming current driving unit selected among the plurality of programming current driving units by a plurality of driving selection signals.

Abstract: A semiconductor memory device prevents a faulty operation of a program operation, and increases the reliability of operation. The semiconductor memory device includes a unit cell including a memory element configured to have a different resistance value in response to data, and a write driver configured to output a program current and voltage for programming the unit cell in response to a test signal.

Abstract: A phase change memory apparatus includes a global bit line and an internal power generation circuit. The global bit line is configured to integratedly control a plurality of bit lines. The internal power generation circuit is configured to supply an internal voltage while the global bit line is discharged and configured to control the internal voltage after the global bit line is discharged, when a deep power down mode signal is enabled.

Abstract: A phase change memory device includes a plurality of intersecting bit lines and word lines. A cell array including a plurality of unit phase change resistance cells is formed at intersections of the plurality of bit lines and the plurality of word lines. A plurality of sub word line driving units are configured to drive the word lines in response to a plurality of sub word line signals. A plurality of main word line driving units are configured to drive the sub word line driving units in response to a main word line signal. A precharge unit is configured to precharge the word lines. In the phase change memory device, the driving units are decentralized.

Abstract: Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data.