Patents by Inventor Hyuek Jae Lee
Hyuek Jae Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10535534Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.Type: GrantFiled: May 4, 2017Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Tae-Je Cho, Hyuek-Jae Lee, Cha-Jea Jo
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Publication number: 20170330767Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.Type: ApplicationFiled: May 4, 2017Publication date: November 16, 2017Inventors: Un-Byoung Kang, Tae-Je CHO, Hyuek-Jae Lee, Cha-Jea Jo
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Publication number: 20160082569Abstract: A retainer for a wafer carrier comprising: a body including a plurality of slots configured to receive side surfaces of wafers; and for each of the slots, a supporting structure formed on a sidewall of the slot and configured to make contact with the side surfaces of a corresponding wafer, the supporting structure being spaced apart from an upper corner of the side surface of the corresponding wafer.Type: ApplicationFiled: June 2, 2015Publication date: March 24, 2016Inventors: Sang-Hyun BAE, Kyu-Dong JUNG, Il-Hwan KIM, Jung-Hwan KIM, Hyuek-Jae LEE, Tae-Je CHO
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Publication number: 20140252626Abstract: A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a wafer, a plurality of semiconductor chips each having a connection pad and being stacked on the wafer, resin layers formed to expose top surfaces of the connection pads and to cover lateral surfaces and top surfaces of the semiconductor chips, through lines formed in at least one side of opposite sides of each of the semiconductor chips, to be spaced apart from the semiconductor chips, and to extend in a first direction, and redistribution lines arranged between the through lines, formed to extend in a second direction on the resin layers, and connected to the connection pads, wherein the through lines and the redistribution lines include barrier layers formed on lateral surfaces and bottom surfaces of the through lines and the redistribution lines, and conductive layers formed on the barrier layers.Type: ApplicationFiled: March 11, 2014Publication date: September 11, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung KANG, Hyuek-Jae LEE, Chung-Sun LEE
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Patent number: 8563349Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.Type: GrantFiled: October 26, 2011Date of Patent: October 22, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Yun Myung, Hyuek-Jae Lee, Ji-Sun Hong, Tae-Je Cho, Un-Byoung Kang, Hyung-Sun Jang, Eun-Mi Kim, Jung-Hwan Kim, Tae-Hong Min
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Patent number: 8304288Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.Type: GrantFiled: June 8, 2011Date of Patent: November 6, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hyuek-Jae Lee, Ji-Sun Hong, Tae-Je Cho, Jong-Yun Myung, Young-Bok Kim, Hyung-Sun Jang, Eun-Mi Kim
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Publication number: 20120156823Abstract: A method of forming a semiconductor device includes preparing a semiconductor substrate having a plurality of chips formed thereon and a scribe lane disposed between the chips, simultaneously forming a groove having a first depth in the scribe lane, and a through hole penetrating the chips and having a second depth. The chips are separated along the groove. The first depth is smaller than the second depth.Type: ApplicationFiled: October 26, 2011Publication date: June 21, 2012Inventors: Jong-Yun MYUNG, Hyuek-Jae Lee, Ji-Sun Hong, Tae-Je Cho, Un-Byoung Kang, Hyung-Sun Jang, Eun-Mi Kim, Jung-Hwan Kim, Tae-Hong Min
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Publication number: 20110306167Abstract: A method of packaging a semiconductor device may include providing a semiconductor substrate including first and second spaced apart semiconductor chip areas, and adhering a cover on the first and second spaced apart semiconductor chip areas of the semiconductor substrate. A scribe line may be formed through the semiconductor substrate between the first and second semiconductor chip areas with a semiconductor bridge pattern remaining connected between the first and second spaced apart semiconductor chip areas after forming the scribe line. The cover and the semiconductor bridge pattern may then be cut after forming the scribe line.Type: ApplicationFiled: June 8, 2011Publication date: December 15, 2011Inventors: Hyuek-Jae Lee, Ji-Sun Hong, Tae-je Cho, Jong-Yun Myung, Young-Bok Kim, Hyung-Sun Jang, Eun-Mi Kim
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Patent number: 7884392Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.Type: GrantFiled: January 29, 2009Date of Patent: February 8, 2011Inventors: Hyuek-Jae Lee, Tae-Je Cho, Yong-Hwan Kwon, Un-Byoung Kang, Chung-Sun Lee, Woon-Seong Kwon, Hyung-Sun Jang
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Publication number: 20090256931Abstract: A camera module, a method of manufacturing the same, and an electronic system having the same are provided. The camera module includes an image sensor chip having an active plane and a backside, a ground wiring extending from a sidewall of the image sensor chip to the backside, a lens structure having a light detector with at least one lens stacked on the active plane, and a conductive housing extending to the ground wiring along with an outer wall of the lens structure excluding the light detector.Type: ApplicationFiled: March 12, 2009Publication date: October 15, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Chung-Sun Lee, Yong-Hwan Kwon, Un-Byoung Kang, Hyuek-Jae Lee, Woon-Seong Kwon, Hyung-Sun Jang
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Publication number: 20090200632Abstract: One embodiment exemplarily described herein can be characterized as an image sensor including a substrate having a front surface and a rear surface; a photoelectric converting portion on the front surface of the substrate; a through via extending through the substrate, wherein the through via is electrically connected to the photoelectric converting portion; an external connection terminal on the rear surface of the substrate, wherein the external connection terminal is connected to the through via; and a light shading layer formed on a portion of the rear surface of the substrate, wherein the light shading layer is substantially opaque with respect to an external light. In some embodiments, the portion of the rear surface of the substrate on which the light shading layer is formed is not overlapped by the through via or the external connection terminal.Type: ApplicationFiled: January 29, 2009Publication date: August 13, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek-Jae LEE, Tae-Je CHO, Yong-Hwan KWON, Un-Byoung KANG, Chung-Sun LEE, Woon-Seong KWON, Hyung-Sun JANG
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Patent number: 7034989Abstract: Disclosed are an apparatus and method for converting the wavelength of an optical signal using a multi-mode Fabry-Perot laser diode. The apparatus controls polarization of an external pump optical signal to output a TE polarized pump optical signal, and controls polarization of a probe optical signal to output a TM polarized probe optical signal. The apparatus couples the TM polarized probe optical signal and TE polarized pump optical signal irrespective of the polarization of the optical signals. The apparatus finely controls the polarization of the pump optical signal and the polarization of the probe optical signal such that they conform to TE and TM modes of the Fabry-Perot laser diode, respectively.Type: GrantFiled: April 28, 2004Date of Patent: April 25, 2006Assignees: Information and Communications University Educational Foundation, Samsung Electronics Co., Ltd.Inventors: Hark Yoo, Hyuek Jae Lee, Yong Deok Jeong, Yong Hyub Won, Min Ho Kang
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Patent number: 6934348Abstract: Disclosed is a device for recovering a burst-mode clock. The burst-mode clock recovery device includes a delay unit and a logic element. A reference clock is produced by implementing a logic operation with respect to a signal output from signal forming device and a signal output from the signal forming device and delayed by a delay unit. A duty of a final output signal is corrected by implementing and AND operation with respect to the generated reference clock and an output from feedback device.Type: GrantFiled: October 23, 2001Date of Patent: August 23, 2005Assignee: Roswin Co., Ltd.Inventors: Hyuek-Jae Lee, Sung-Yong Hong
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Patent number: 6902660Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole in the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.Type: GrantFiled: August 30, 2002Date of Patent: June 7, 2005Assignee: Korea Advanced Institute of Science and TechnologyInventors: Hyuek Jae Lee, Jin Yu
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Publication number: 20040035711Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole to the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.Type: ApplicationFiled: August 30, 2002Publication date: February 26, 2004Inventors: Hyuek Jae Lee, Jin Yu
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Patent number: 6594053Abstract: An apparatus for controlling cycles of optical pulse streams based on a time correlation is disclosed. The feedback optical pulses and the input optical pulses are subjected to a time interleaving so as to make them not overlapped together, and then they are subjected to a time correlation, thereby considerably reducing the polarized beam dependence of the input optical pulse streams. The apparatus includes a clock generating means for generating clocks, and an optical pulse generating means for receiving the clocks from the clock generating means to generate optical pulses in synchronization with the pulses of the clock generating means. An input optical pulse distributing means distributes the feedback optical pulses of an output optical pulse distributing means, and distributes the optical pulses of the optical pulse generating means.Type: GrantFiled: November 2, 1999Date of Patent: July 15, 2003Assignee: Electronics and Telecommunications Research InstituteInventors: Hyuek Jae Lee, Hae Geun Kim, Jee Yon Choi, Sung Wan Kim
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Publication number: 20020090044Abstract: Disclosed is a device for recovering a burst-mode clock. The burst-mode clock recovery device includes a delay unit and a logic element. A reference clock is produced by implementing a logic operation with respect to a signal output from signal forming means and a signal output from the signal forming means and delayed by a delay unit. A duty of a final output signal is corrected by implementing an AND operation with respect to the generated reference clock and an output from feedback means.Type: ApplicationFiled: October 23, 2001Publication date: July 11, 2002Inventors: Hyuek-Jae Lee, Sung-Yong Hong
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Patent number: 6097529Abstract: An apparatus for enhancing the extinction ratio in an optical NRZ-to-RZ converting system, and an optical modulation system, are disclosed. The extinction ratio is improved by using an optical fiber loop mirror together with optical amplifiers. The apparatus for enhancing the extinction ratio includes a variable coupling means for receiving external signals to split them to respective terminals of a loop mirror. A variable optical delaying means delays the phases of the signals after their dispersion by the variable coupling means. An optical amplifying means positioned asymmetrically smaller than a bit time of an RZ signal pattern inputted slightly departed from the center of the loop mirror amplifies the optical intensity, and varies the refractive index so as to cause a phase delay. A polarization adjusting means adjusts the polarization of the optical signals, and an optical band pass filtering means removes noises from signals outputted from the loop mirror.Type: GrantFiled: August 21, 1998Date of Patent: August 1, 2000Assignee: Electronics and Telecommunications Research InstituteInventors: Hyuek Jae Lee, Kwang Joon Kim, Hye Young Kim, Seok Youl Kang