Abstract: A method of generating data is provided. The method includes providing, by a peak comparator, a searcher enable signal and peak comparator output data based on result values that are generated by multiplying an input signal having a plurality of levels and a predetermined convolution pattern, providing by a start pattern searcher, a data determiner enable signal by comparing the peak comparator output data and a predetermined start pattern according to the searcher enable signal; and providing, by a data determiner, result data corresponding to the input signal based on the data determiner enable signal, the input signal and a predetermined filter mask pattern.

Abstract: A receiver of a near field communication device includes a local oscillator, a first channel, and a second channel. The local oscillator may be configured to generate a first local oscillating signal. The first channel may be configured to process an input signal by mixing the input signal with the first local oscillating signal. The second channel may be configured to process the input signal by mixing the input signal with a second local oscillating signal that has a phase difference of 90 degrees with respect to the first local oscillating signal. Each of the first and second channels may include a comparator unit that includes a comparator configured to compare, in a comparator mode, an amplifier output signal with a reference voltage whose level increases in a step-wise manner and the comparator unit may be configured to set a level of the reference voltage to be used in a normal mode based on an output signal of the comparator.

Abstract: A method of generating data is provided. The method includes providing, by a peak comparator, a searcher enable signal and peak comparator output data based on result values that are generated by multiplying an input signal having a plurality of levels and a predetermined convolution pattern, providing by a start pattern searcher, a data determiner enable signal by comparing the peak comparator output data and a predetermined start pattern according to the searcher enable signal; and providing, by a data determiner, result data corresponding to the input signal based on the data determiner enable signal, the input signal and a predetermined filter mask pattern.

Abstract: A data receiver for near field communication (NFC) includes an analog receiving unit and a digital processing unit. The analog receiving unit is configured to output one of received first data and modified received second data, according to an operation mode, the modified received second data being in-phase data and quadrature-phase data generated based on the received second data. The digital processing unit is configured to, determine a sampling characteristic of a first channel based on a first offset value, determine a sampling characteristic of a second channel based on a second offset value, detect a communication protocol of the received first data based on the first and second channels, and decode and store the received first data based on the detected communication protocol of the first data.

Abstract: A receiver of a near field communication device includes a local oscillator, a first channel, and a second channel. The local oscillator may be configured to generate a first local oscillating signal. The first channel may be configured to process an input signal by mixing the input signal with the first local oscillating signal. The second channel may be configured to process the input signal by mixing the input signal with a second local oscillating signal that has a phase difference of 90 degrees with respect to the first local oscillating signal. Each of the first and second channels may include a comparator unit that includes a comparator configured to compare, in a comparator mode, an amplifier output signal with a reference voltage whose level increases in a step-wise manner and the comparator unit may be configured to set a level of the reference voltage to be used in a normal mode based on an output signal of the comparator.

Abstract: A method of receiving wireless data is provided. The method includes generating a plurality of local clocks having different delayed phases with respect to a carrier wave during a carrier wave period and receiving a data packet using the plurality of local clocks. The plurality of local clocks includes at least a first local clock and a second local clock. The first local clock has a 0 degree delayed phase with respect to the carrier wave. The second local clock has a 90 degree delayed phase with respect to the carrier wave.

Abstract: A data receiver for near field communication (NFC) includes an analog receiving unit and a digital processing unit. The analog receiving unit is configured to output one of received first data and modified received second data, according to an operation mode, the modified received second data being in-phase data and quadrature-phase data generated based on the received second data. The digital processing unit is configured to, determine a sampling characteristic of a first channel based on a first offset value, determine a sampling characteristic of a second channel based on a second offset value, detect a communication protocol of the received first data based on the first and second channels, and decode and store the received first data based on the detected communication protocol of the first data.

Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

Abstract: A type-A demodulator comprising a first rectifier configured to rectify a radio frequency (RF) signal received through an antenna and output a first voltage, a second rectifier configured to rectify the voltage of the RF signal received through the antenna and output a second voltage having a different voltage level than the first voltage, and a pause data detector configured to compare the first voltage with the second voltage and detect received pause data.

Abstract: A smart card system may include a smart card; and a smart card reader configured to communicate via a smart card protocol with the smart card, wherein the smart card includes a modulus counter that generates an operation clock of the smart card by receiving an external clock complying with the smart card protocol from the smart card reader, dividing the external clock a first and a second time to generate a first and a second dividing clock, counting the first dividing clock for A number of times, and counting the second dividing clock for N-A number of times.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.

Abstract: A type-A demodulator comprising a first rectifier configured to rectify a radio frequency (RF) signal received through an antenna and output a first voltage, a second rectifier configured to rectify the voltage of the RF signal received through the antenna and output a second voltage having a different voltage level than the first voltage, and a pause data detector configured to compare the first voltage with the second voltage and detect received pause data.

Abstract: A smart card system may include a smart card; and a smart card reader configured to communicate via a smart card protocol with the smart card, wherein the smart card includes a modulus counter that generates an operation clock of the smart card by receiving an external clock complying with the smart card protocol from the smart card reader, dividing the external clock a first and a second time to generate a first and a second dividing clock, counting the first dividing clock for A number of times, and counting the second dividing clock for N?A number of times.

Abstract: A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the clock signal during a reference time, and to compare the number of pulses with a reference value to provide a comparison result, and to generate a control signal based on the comparison result, where the clock signal generation unit increases or decreases the number of pulses of the clock signal based on the control signal.

Abstract: Provided is a smart card for communicating with a host computer through a universal serial bus (USB). The smart card includes an internal clock signal generator to generate an internal clock signal, a period detector to detect a period of the internal clock signal and to generate a control code according to the detected period, and a transmission clock generator to generate a transmission clock signal which varies from the internal clock signal according to the control code. The smart card transfers data in sync with the transmission clock signal.

Abstract: An integrated circuit card includes an interface block for performing an interface function with the external devices and a power controller for controlling power of a security integrated circuit for detecting if an operational environment is in an abnormal state, the power controller periodically and selectively applies power to the security integrated circuit. Thus, power consumption is reduced in the integrated circuit card; and a stable operation of the integrated circuit card which contactlessly communicates with the external devices can be secured with an extended communication distance.

Abstract: A clock signal generator for a USB device. The clock signal generator includes a control circuit and a clock generator that does not need to include a crystal oscillator. The control circuit counts the cycle of the clock signal during the period between two sync signals successively inputted, and generates a frequency control signal corresponding to the count value. The clock generator generates the clock signal with a frequency corresponding to the frequency control signal. The clock signal generator can generate a clock signal that is suitable for the data transfer rate defined, in the USB specification. In addition, the clock; signal generator can generate an RX clock signal so that an RX data signal can be recovered with its energy being stable.

Abstract: A frequency detecting circuit and method and a semiconductor apparatus including the frequency detecting circuit, in which the frequency detecting circuit includes an edge detecting circuit, a clock signal generating circuit, and a determination circuit. The edge detecting circuit detects an edge of an input clock signal. The clock signal generating circuit generates a selection clock signal, which is a periodic pulse signal, in response to the detected edge. The determination circuit generates a frequency detection signal based on the number of occurrences of the selection clock signal in a period of the clock signal. The semiconductor apparatus includes the above-described frequency detecting circuit and a processor resetting the semiconductor apparatus in response to the frequency detection signal. Since a frequency is detected every half period, that is every high/low level period, of the clock signal in a digital manner, the reliability and the accuracy of frequency detection is improved.

Abstract: An integrated circuit card includes an interface block for performing an interface function with the external devices and a power controller for controlling power of a security integrated circuit for detecting if an operational environment is in an abnormal state, the power controller periodically and selectively applies power to the security integrated circuit. Thus, power consumption is reduced in the integrated circuit card; and a stable operation of the integrated circuit card which contactlessly communicates with the external devices can be secured with an extended communication distance.