Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.

Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.

Abstract: A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data.

Abstract: A non-volatile memory device may include a memory cell array, a page buffer, a column decoder, a column selection circuit and a repair circuit. The memory cell array includes normal memory cells and redundancy memory cells. In one example, the page buffer may load normal data and redundancy data from the memory cell array. The column decoder may generate a normal column selection signal and a redundancy column selection signal in response to a column address. The column selection circuit may select the normal data and redundancy data in response to the normal column selection signal and redundancy column selection signal. The repair circuit may then output one of the normal data and redundancy data.