Abstract: A method for pre-lithiation of a negative electrode is disclosed, including the steps of: producing a lithium metal laminate which includes i) lithium metal foil; and ii) a buffer layer including carbonaceous material particles, inorganic compound particles, polymer compound particles or their combination, and coated on one surface of the lithium metal foil; producing a negative electrode including a negative electrode current collector, and a negative electrode active material layer formed on at least one surface of the negative electrode current collector; and laminating the lithium metal laminate with the negative electrode in such a manner that the buffer layer of the lithium metal laminate is in contact with the negative electrode active material layer. A lithium metal laminate used for the method is also provided. The pre-lithiation of a negative electrode that includes a buffer layer reduces the problem of rapid volumetric swelling occurring.

Abstract: Disclosed is a plasma generator. The plasma generator may include a gripping portion including at least one interface unit configured to receive an input from a user; a head portion including a plasma generating portion configured to generate the plasma; a first cartridge configured to detachably couple at a first end of the head portion and generate the plasma over a predetermined region; and a light irradiation portion provided at a second end of the head portion.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A display includes: a display panel; and a panel bottom sheet disposed below the display panel, the panel bottom sheet including: a first heat dissipation layer; a second heat dissipation layer over the first heat dissipation layer, including a first opening formed completely through the second heat dissipation layer in a thickness direction; a heat dissipation coupling interlayer between the first heat dissipation layer and the second heat dissipation layer, and a heat dissipation substrate on the second heat dissipation layer.

Abstract: A method of preparing a negative electrode for a lithium secondary battery, which includes forming a negative electrode mixture layer including a negative electrode active material on a negative electrode current collector, disposing lithium metal powder on at least a part of the negative electrode mixture layer, pressing the negative electrode mixture layer on which the lithium metal powder is disposed, wetting the pressed negative electrode mixture layer with a first electrolyte solution, and drying the wet negative electrode mixture layer. A battery including the negative electrode of the present invention has enhanced rapid charge/discharge characteristics and enhanced lifespan characteristics.

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

Abstract: A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.

Abstract: A computer-implemented method includes receiving, by a computing device, input activations and determining, by a controller of the computing device, whether each of the input activations has either a zero value or a non-zero value. The method further includes storing, in a memory bank of the computing device, at least one of the input activations. Storing the at least one input activation includes generating an index comprising one or more memory address locations that have input activation values that are non-zero values. The method still further includes providing, by the controller and from the memory bank, at least one input activation onto a data bus that is accessible by one or more units of a computational array. The activations are provided, at least in part, from a memory address location associated with the index.

Abstract: A computing unit is disclosed, comprising a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs one or more computations associated with at least one element of a data array, the one or more computations being performed by the MAC operator and comprising, in part, a multiply operation of the input activation received from the data bus and a parameter received from the second memory bank.

Abstract: Disclosed is a power semiconductor device that includes a gate electrode recessed from a first surface of a semiconductor substrate to a second surface, disposed opposite to the first surface, of the semiconductor substrate, an emitter region, including impurities in a first conductive type, disposed in contact with a trench, in which the gate electrode is disposed, and the first surface, a collector region, including impurities in a second conductive type opposite to the first conductive type, disposed in contact with the second surface, a floating region, including the impurities in the second conductive type, extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and a trench emitter region interposed under the gate electrode in the trench.

Abstract: A power semiconductor device includes a plurality of gate electrodes configured to be recessed from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate, the second surface being opposite to the first surface, an emitter region configured to make contact with a trench and the first surface, being provided between respective ones of the plurality of gate electrodes, and including impurities of a first conductive type, a collector region configured to make contact with the second surface, and including second impurities of a second conductive type opposite to the first conductive type, a floating region extending toward the second surface in an extension direction of the trench while surrounding a bottom surface of the trench, and including the second impurities, and a trench emitter region interposed between the plurality of gate electrodes in the trench.

Abstract: A preparation method according to the present invention makes it possible to industrially produce large amounts of highly pure optically active tert-butyl 3-methyl-4-oxopiperidine-1-carboxylate in high yield by use of commercially available reagents and solvents. In addition, the use of novel intermediates according to the present invention makes it possible to produce highly pure optically active tert-butyl 3-methyl-4-oxopiperidine-1-carboxylate in high yield.

Abstract: A hardware accelerator can receive, from a host processor, a slice of input data at a time-step. The hardware accelerator can process the input data using a machine learning model deployed on the hardware accelerator to compute a respective probability among multiple probabilities for each of multiple classes. The respective probability for each class being a likelihood that content in the slice belongs to the class. The hardware accelerator can determine, from the multiple probabilities, a preset number of highest probabilities for the slice of input data. The hardware accelerator can transmit the preset number of highest probabilities for the slice to the host processor. Related apparatus, systems, techniques and articles are also described.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for training giant neural networks. One of the methods includes obtaining data indicating a neural network comprising a plurality of layers; for each layer in a subset of the plurality of layers: assigning a subset of the plurality of computing units to at least partially perform inference computations associated with the layer; determining a memory size and a common memory address for the respective addressable memory unit of each computing unit assigned for the layer; and generating a shared instruction comprising a memory allocation instruction that, when executed by each of the subset of the plurality of computing units, causes the computing unit to store a result of performing inference computations associated with the layer in the determined common memory address with the determined memory size in the addressable memory of the computing unit.

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.

Abstract: One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.

Abstract: A light emitting display device includes a first semiconductor layer; a first gate insulating layer; a first gate conductive layer; a second gate insulating layer; a first data conductive layer; a lower organic layer; a second data conductive layer includes a first anode connection member and a second anode connection member; an upper organic layer; a first anode and a second anode; and a pixel defining layer that includes a first opening and a second opening respectively exposing the first anode and the second anode, wherein the upper organic layer include a first anode connection opening and a second anode connection opening through which the first anode and the second anode are respectively electrically connected with the first anode connection member and the second anode connection member.

Abstract: A hardware accelerator can store, in multiple memory storage areas in one or more memories on the accelerator, input data for each processing time step of multiple processing time steps for processing sequential inputs to a machine learning model. For each processing time step, the following is performed. The accelerator can access a current value of a counter stored in a register within the accelerator to identify the processing time step. The accelerator can determine, based on the current value of the counter, one or more memory storage areas that store the input data for the processing time step. The accelerator can facilitate access of the input data for the processing time step from the one or more memory storage areas to at least one processor coupled to the one or more memory storage areas. The accelerator can increment the current value of the counter stored in the register.