Patents by Inventor HYUK WOO KWON

HYUK WOO KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11737256
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 22, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Won Lee, Hyuk-Woo Kwon, Ik-Soo Kim, Byoung-Deog Choi
  • Publication number: 20230055450
    Abstract: A semiconductor device including a first pad on a substrate extending in a first direction and a second direction, a lower electrode connected to and disposed on the first pad, first to third supporter layers disposed on a side wall of the lower electrode and sequentially spaced apart from each other in a third direction perpendicular to the first direction and the second direction, a dielectric film disposed on the lower electrode and the first to third supporter layers, and an upper electrode disposed on the dielectric film. At least one of a side wall of the lower electrode between the first supporter layer and the second supporter layer, and a side wall of the lower electrode between the second supporter layer and the third supporter layer includes a first portion including protrusions extending in the first direction and includes a second portion including no protrusions.
    Type: Application
    Filed: June 16, 2022
    Publication date: February 23, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong Min CHOO, Hyuk Woo KWON, Dong Woo KIM, Byoung Deog CHOI
  • Publication number: 20220005808
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
    Type: Application
    Filed: September 16, 2021
    Publication date: January 6, 2022
    Inventors: Jun-Won LEE, Hyuk-Woo KWON, Ik-Soo KIM, Byoung-Deog CHOI
  • Patent number: 11133317
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Won Lee, Hyuk-Woo Kwon, Ik-Soo Kim, Byoung-Deog Choi
  • Publication number: 20200152634
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
    Type: Application
    Filed: May 23, 2019
    Publication date: May 14, 2020
    Inventors: Jun-Won LEE, Hyuk-Woo KWON, Ik-Soo KIM, Byoung-Deog CHOI
  • Patent number: 10586709
    Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Min Ko, Hyuk Woo Kwon, Jun-Won Lee
  • Publication number: 20190172717
    Abstract: Methods for fabricating a semiconductor device are provided including sequentially forming a first hard mask layer, a second hard mask layer and a photoresist layer on a target layer, patterning the photoresist layer to form a photoresist pattern, sequentially patterning the second hard mask layer and the first hard mask layer using the photoresist pattern as an etching mask to form a first hard mask pattern and a second hard mask pattern on the first hard mask pattern, and etching the target layer using the first hard mask pattern and the second hard mask pattern as an etching mask, wherein the second hard mask layer includes impurity-doped amorphous silicon.
    Type: Application
    Filed: July 9, 2018
    Publication date: June 6, 2019
    Inventors: YOUNG-MIN KO, HYUK WOO KWON, JUN-WON LEE