Abstract: A method of manufacturing a semiconductor device includes placing a wafer in a plasma chamber, the chamber including a first power generator configured to generate plasma ions in the chamber, and a second power generator configured to accelerate the plasma ions toward the wafer, generating a radio frequency (RF) signal having a repeated periodic sinusoidal waveform in an on state and a steady off state by the first power generator, and generating a direct current (DC) bias signal having a repeated periodic non-sinusoidal waveform in an on state and a steady off state by the second power generator. The RF signal and the DC bias signal are offset from each other. The method further includes performing a plasma process on a layer on the wafer, using the RF signal and DC bias signal.

Abstract: A semiconductor device includes an active region on a substrate, a plurality of channel layers spaced apart from each other, a gate structure on the substrate, a source/drain region on at least one side of the gate structure, and a contact plug connected to the source/drain region. The contact plug includes a metal-semiconductor compound layer and a barrier layer on the metal-semiconductor compound layer. The contact plug includes a first inclined surface and a second inclined surface positioned where the metal-semiconductor compound layer and the barrier layer directly contact each other. The barrier layer includes first and second ends protruding towards the gate structure. The first and second ends are positioned at a level higher than an upper surface of an uppermost channel layer. An uppermost portion of the metal-semiconductor compound layer is positioned at a level higher than an upper surface of the source/drain region.

Abstract: An integrated circuit device includes a first conductive pattern on a substrate, a second conductive pattern surrounding at least a portion of the first conductive pattern and covering a lower portion of a sidewall of the first conductive pattern, an upper insulating structure on the first conductive pattern and the second conductive pattern, and an upper conductive pattern extending in a vertical direction through the upper insulating structure. The upper conductive pattern includes a main plug portion overlapping the first conductive pattern and the second conductive pattern in the vertical direction, and a vertical extension portion extending from a local region of the main plug portion toward the substrate, the vertical extension portion covering an upper portion of the sidewall of the first conductive pattern and overlapping the second conductive pattern in the vertical direction.

Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern and a source/drain pattern on the active pattern, wherein the channel pattern is connected to the source/drain pattern, a gate electrode on the channel pattern, and a gate contact connected to a top surface of the gate electrode, wherein the gate contact includes a capping layer directly contacting the top surface of the gate electrode and a metal layer on the capping layer, wherein the capping layer and the metal layer include the same metal, a concentration of oxygen in the metal layer ranges from between about 2 at % to about 10 at %, and a maximum concentration of oxygen in the capping layer ranges from between about 15 at % to about 30 at %.

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

Abstract: A variable frequency and non-sinusoidal power generator includes a pulse module circuit, a slope module circuit, and first and second cooling systems. The pulse module circuit and the slope module circuit includes control switches, and generates at least one of a output currents and a output voltages by selectively turning on/off the control switches based on control signals. The first and second cooling systems are disposed at first and second sides of the control switches. A bias power having a variable frequency and a non-sinusoidal waveform is generated based on the control signals, at least one of the output currents and the output voltages.

Abstract: A high voltage power supply apparatus includes a high voltage direct current voltage source, a power switch configured to apply an output of the high voltage direct current voltage source to process equipment, and a sensing circuit unit including a sensor unit including a sensor and at least one operational amplifier, a reference voltage detection unit connected to a node between the sensor and the at least one operational amplifier, and a digital signal processing unit, wherein the sensing circuit unit is connected to an output terminal through which an output of the high voltage direct current voltage source is applied to the process equipment.

Abstract: A variable frequency and non-sinusoidal power generator includes a pulse module circuit, a slope module circuit, and first and second cooling systems. The pulse module circuit and the slope module circuit includes control switches, and generates at least one of a output currents and a output voltages by selectively turning on/off the control switches based on control signals. The first and second cooling systems are disposed at first and second sides of the control switches. A bias power having a variable frequency and a non-sinusoidal waveform is generated based on the control signals, at least one of the output currents and the output voltages.

Abstract: A wafer processing apparatus includes a chamber, and a voltage waveform generator configured to accelerate plasma ions of the chamber, the voltage waveform generator includes: a pulse circuit configured to apply a chamber voltage, which is a pulse voltage, to the chamber by adjusting a chamber current applied to the chamber; and a slope circuit configured to generate a slope in an on-duty of the chamber voltage, which is the pulse voltage, and the pulse circuit includes a first inductive element configured to store a first internal current.

Abstract: Smart USB plug detection is disclosed. In some embodiments, a battery charger identification chip includes circuitry configured to determine whether an external USB device has been plugged into a USB port of an associated system while the system is in a sleep mode and includes a pin configured to output a control signal indicating whether an external USB device is plugged into the system, wherein when an external USB device is plugged into the system the control signal facilitates powering on a current limit switch that is otherwise powered off during the sleep mode and wherein the current limit switch facilitates regulated delivery of current to the plugged in external USB device.

Abstract: An image output correcting device includes an output unit to process a first image and to output the processed first image as a second image, an input unit to receive a part of the second image output, a computation unit to compute a depth information of a surface on which the image is outputted by comparing the first image and the second image input to the input unit, and a control unit to generate a third image using the depth information to be outputted. A method for correcting an image output on a surface using depth information includes processing a first image, outputting a second image, computing depth information of a surface to which the second image is outputted by comparing the first image and the second image, and generating a third image using the depth information and outputting the third image.

Abstract: An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to either the second signal or a predetermined time period expiring.

Abstract: A line driver and a method for driving a line are disclosed. The line driver includes a first current device configured to initiate a change in the state of the line and a second current device configured to substantially complete the change. The first current device provides a first current and the second current device provides a second current that is smaller than the first current.