Abstract: A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer.

Abstract: A trench isolation method is provided. In the trench isolation method, a pad oxide film, an oxidative film and an etching mask film are formed on a semiconductor substrate in sequence, and then a trench is formed in a field region of the semiconductor substrate. A oxide film is formed at the inner wall of the trench and the side walls of the oxidative film by oxidizing the semiconductor substrate. After filling the trench with a dielectric material, the pad oxide film, oxidative film and etching mask film formed in the active region are removed.

Abstract: A method for manufacturing a semiconductor memory device in which a bit line and a storage electrode of a capacitor are connected to an active area of a semiconductor substrate, respectively, via a contact pad formed in a self-aligning manner. The method includes the steps of forming gate electrodes on the semiconductor substrate, the gate electrodes being covered with a nitride spacer. Then, a thermal oxide layer is formed on the exposed surface of the semiconductor substrate between the gate electrodes. Then, an etch stop layer is formed on the entire surface of the resultant structure having the thermal oxide layer to an appropriate thickness such that the space between the gate electrodes is not buried. Then, a first interlayer dielectric (ILD) film covering the space between the gate electrodes and the top of the gate electrodes is formed, and the first ILD film is then patterned to form a landing pad hole which exposes the spacer and the etch stop layer.

Abstract: A semiconductor device using a self-aligned contact and a method for manufacturing the same is disclosed. A gate electrode having a first spacer formed on the sidewalls thereof is formed on a semiconductor substrate. Active regions which are spaced apart from each other by the gate electrode are formed in the semiconductor substrate. A bitline having a second spacer formed on the sidewalls thereof is formed on the gate electrode and the active regions. A self-aligned contact is formed on the active regions and a first pad electrode connected with the active region through the contact is formed between the bitlines. A bitline contact is formed on the bitline, and second and third pad electrodes, which are respectively connected with the bitline and the first pad electrode through the bitline contact, are formed on the bitline. Thus, the alignment tolerances of the bitline contact and the storage-node contact are maximized, so that a reliable semiconductor device can be realized.

Abstract: A semiconductor device using a self-aligned contact and a method for manufacturing the same is disclosed. A gate electrode having a first spacer formed on the sidewalls thereof is formed on a semiconductor substrate. Active regions which are spaced apart from each other by the gate electrode are formed in the semiconductor substrate. A bitline having a second spacer formed on the sidewalls thereof is formed on the gate electrode and the active regions. A self-aligned contact is formed on the active regions and a first pad electrode connected with the active region through the contact is formed between the bitlines. A bitline contact is formed on the bitline, and second and third pad electrodes, which are respectively connected with the bitline and the first pad electrode through the bitline contact, are formed on the bitline. Thus, the alignment tolerances of the bitline contact and the storage-node contact are maximized, so that a reliable semiconductor device can be realized.