Abstract: Disclosed is an operating method of an electronic device which simulates a design of an integrated circuit. The method includes detecting, at the electronic device, a power domain structure of the integrated circuit from a register transfer level (RTL) model of the integrated circuit, detecting, at the electronic device, current isolation values of ports of the integrated circuit from the power domain structure of the integrated circuit and an unified power format (UPF) of the integrated circuit, detecting, at the electronic device, reference isolation values of the ports of the integrated circuit, detecting, at the electronic device, reset values of the ports of the integrated circuit, and checking, at the electronic device, isolation errors of the ports of the integrated circuit based on the current isolation values, the reference isolation values, and the reset values.

Abstract: A multiple data transmission method and a multiple data transmission system are disclosed. A multiple data transmission system, according to one embodiment of the present invention, comprises: an identification unit for identifying, from among a plurality of separated networks, a first network to which a transmission device requesting data transmission belongs; a generation unit for generating a data packet by adding a destination address set for the first network as a header to data transmitted from the transmission device; and a transmission unit for transmitting the data packet to a reception device identified by the destination address, through a transmission path which connects the first network and a second network to which the reception device belongs.

Abstract: Provided are a method and a system for transmitting multiple data, in which the method includes receiving a plurality of transmission files for transmission from a transmission device of the first network to a reception device of the second network, and temporarily storing the received files, generating flexible packets by dividing each of the plurality of transmission files by a flexible packet length determined according to size of the files, in which a transmission file in a size smaller than the flexible packet length among the plurality of transmission files is generated as one flexible packet without being divided, loading the flexible packets into a plurality of flexible frames based on a corresponding transmission file priority according to a maximum data transmission size, and transmitting the plurality of flexible frames to the second network.

Abstract: Provided are a method and a system for transmitting multiple data, in which the method includes receiving a plurality of transmission files for transmission from a transmission device of the first network to a reception device of the second network, and temporarily storing the received files, generating flexible packets by dividing each of the plurality of transmission files by a flexible packet length determined according to size of the files, in which a transmission file in a size smaller than the flexible packet length among the plurality of transmission files is generated as one flexible packet without being divided, loading the flexible packets into a plurality of flexible frames based on a corresponding transmission file priority according to a maximum data transmission size, and transmitting the plurality of flexible frames to the second network.

Abstract: A test method for a system on chip, the test method including: receiving a system on chip including a plurality of blocks; booting up the system on chip; storing input values that are input to each of the plurality of blocks, while booting up the system on chip; and performing a test on a first block among the plurality of blocks, wherein performing the test on the first block includes: disabling components of each of the plurality of blocks except the first block, and inputting a first input value to the first block to initialize the first block, wherein the first input value is one of the stored input values that was input to the first block while booting-up the system on chip.

Abstract: A test method for a system on chip, the test method including: receiving a system on chip including a plurality of blocks; booting up the system on chip; storing input values that are input to each of the plurality of blocks, while booting up the system on chip; and performing a test on a first block among the plurality of blocks, wherein performing the test on the first block includes: disabling components of each of the plurality of blocks except the first block, and inputting a first input value to the first block to initialize the first block, wherein the first input value is one of the stored input values that was input to the first block while booting-up the system on chip.

Abstract: A connector is provided. The connector includes a connector body formed with a terminal portion, a locking body slidably coupled to the connector body, and a spring including a first leg portion fixed in position inside the connector body and a second leg portion making contact with the locking body. The spring is configured to apply a restoring force to the locking body in a direction in which the second leg portion is moved away from the first leg portion.

Abstract: A system-on-chip (SoC) includes: a plurality of processors configured to store respective debugging information in response to respective information extraction commands received in a deadlock state, the plurality of processors having different architectures; a system bus connected to the plurality of processors; and an SoC manager configured to generate the respective information extraction commands differently according to an architecture of each of the plurality of processors in response to detecting occurrence of the deadlock state, and transmit the respective information extraction commands to the plurality of processors through a bus separate from the system bus.

Abstract: A connector is provided. The connector includes a connector body formed with a terminal portion, a locking body slidably coupled to the connector body, and a spring including a first leg portion fixed in position inside the connector body and a second leg portion making contact with the locking body. The spring is configured to apply a restoring force to the locking body in a direction in which the second leg portion is moved away from the first leg portion.

Abstract: A system-on-chip (SoC) includes: a plurality of processors configured to store respective debugging information in response to respective information extraction commands received in a deadlock state, the plurality of processors having different architectures; a system bus connected to the plurality of processors; and an SoC manager configured to generate the respective information extraction commands differently according to an architecture of each of the plurality of processors in response to detecting occurrence of the deadlock state, and transmit the respective information extraction commands to the plurality of processors through a bus separate from the system bus.

Abstract: Disclosed are a power connector of a thermostat and a manufacturing method thereof.

Abstract: Disclosed are a power connector of a thermostat and a manufacturing method thereof.

Abstract: A corner spring for color CRT includes a first arm where a coupling hole is formed to mate with a stud pin inside the panel, a second arm coupled with an outer face of the frame for supporting the shadow mask, and a welding portion where the first and second arms are welded to each other. The length(L) of movable piece that is from the welding portion to bent portion of the first arm, is represented as 1.08S≦L≦1.75S to the distance (S) from a center of spring hole in a stud pin coupling portion of the first arm to a frame contacting portion of the second arm. The distance (H) between a central axis of the welding portion and the frame welding portion of the second arm is expressed as H≦0.668S.