Abstract: A semiconductor apparatus includes an internal voltage generation circuit and a control circuit. The internal voltage generation circuit includes a plurality of sub-circuits that receive an external voltage as an input and generate at least one internal voltage based on the external voltage. The control circuit determines where the external voltage falls within a range between a minimum operating voltage and a target operating voltage according to power information and a built-in lookup table and controls the plurality of sub-circuits according to a result of the determination.

Abstract: The present disclosure provides digital rear mirror device for providing information related to lane change of vehicle and operating method of the same. In the present disclosure, the digital rear mirror device is mounted on the vehicle and configured to obtain a rear image while the vehicle is traveling, recognize at least one other vehicle in an adjacent lane from the rear image, determine whether the other vehicle is within a reference distance from the vehicle using the rear image, and provide information related to lane change to the adjacent lane while displaying the rear image if the other vehicle is within the reference distance.

Abstract: The present disclosure provides a video processing system for providing digital rear view monitoring and digital video recording in a vehicle, and electronic devices and operating methods of the same. In the present disclosure, the video processing system is configured to receive and store a front view video and a rear view video of the vehicle, and to display the rear view video on a digital rear mirror module. According to a first example embodiment, the video processing system may be implemented with a first electronic device configured to display the rear view video on the digital rear mirror module, and a second electronic device configured to store the front view video and the rear view video. According to a second example embodiment, the video processing system may be implemented with a single electronic device.

Abstract: The present disclosure provides a digital rear mirror device for easy operation based on a button or a sensor and an operating method of the same. In the present disclosure, the digital rear mirror device may be configured to, in response to at least one button arranged on at least one edge of a display module, display identification information on an operation function assigned to the button through the display module. Here, the button may include at least one of a physical button and a touch button. In the present disclosure, the digital rear mirror device may be configured to switch the display module based on a signal detected through at least one sensor that is arranged on at least one edge of the display module. Here, the sensor may include at least one of a motion sensor, a proximity sensor, and a touch sensor.

Abstract: The present disclosure provides an electronic toll collection system (ETCS)-supporting integrated digital rear mirror device and an operating method thereof. According to an example embodiment, the digital rear mirror device may include a digital rear mirror module configured to provide a rear view of a vehicle within a single housing and an ETCS module for electronic toll collection for the vehicle. A substrate of the digital rear mirror module and a substrate of the ETCS module may be separately arranged rather than being stacked within the digital rear mirror device. According to another example embodiment, the ETCS module may transmit information received from an external device to the digital rear mirror module, and the digital rear mirror module may display the information while providing the rear view. Here, the information may include at least one of billing information, event information, traffic information, environmental information, and disaster situation information.

Abstract: The present disclosure provides a digital rear mirror device capable of adjusting an angle of view while driving a vehicle and an operating method of the same. In the present disclosure, the digital rear mirror device is mounted to a vehicle and is configured to acquire driving information of the vehicle while driving the vehicle, to adjust an angle of view for a rear view video of the vehicle based on the driving information, and to display the rear view video according to the angle of view. The driving information may include at least one of speed information indicating a speed of the vehicle, steering information related to steering of the vehicle, and reverse information indicating whether the vehicle is reversing. The digital rear mirror device may expand or reduce the angle of view based on the driving information, or may move the center of the angle of view.

Abstract: Provided are an electronic device for performing an integrated multi-function using a single rear view image of a vehicle and an operating method thereof. Herein, the electronic device is configured to receive a rear view image from a camera device and to process the rear view image to a plurality of target images for a plurality of functions. For a function of a digital image recording system function, the electronic device may store the rear view image as a first target image. For an around view monitoring function, the electronic device may display a portion of the rear view image as a second target image that is a portion of an around view image around the vehicle. For a digital rear view monitoring function, the electronic device may display a portion of the rear view image on a digital rear mirror as a third target image.

Abstract: According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.

Abstract: A substrate treatment apparatus includes a process chamber including a substrate treatment space and a disk on which a substrate is seated; and a showerhead provided on the process chamber, the showerhead including: a body; an inlet space in which a fluid is configured to flow through; and a plurality of spray holes provided on a lower surface of the body and configured to spray the fluid toward a substrate, where the plurality of spray holes are inclined at an angle with respect to the lower surface of the body.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.

Abstract: A memory device including a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit is configured to generate a plurality of operating voltages used in a memory operation, based on a target pump clock, and perform the memory operation by using the plurality of operating voltages. The control logic is configured to select the target pump clock among a plurality of pump clocks, based on a number of data bits which selected memory cells on which the memory operation is to be performed among the plurality of memory cells store, and control the peripheral circuit to perform the memory operation on the selected memory cells.

Abstract: A memory device may include: a memory cell array including a plurality of planes; and a voltage generation circuit including a master pump component and at least one or more sub-pump components that respectively correspond to the planes. During an interleaved operation, the master pump component may generate a first output voltage in response to a first pump clock, and the sub-pump components may generate second output voltages in response to second pump clocks. The master pump component and the sub-pump components may respectively provide the first output voltage and the second output voltages to the corresponding planes. During a non-interleaved operation, the master pump component and the sub-pump components may generate the first output voltage in response to the first pump clock and provide the first output voltage to a selected plane of the plurality of planes.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory block, a voltage generation circuit configured to operate in a first mode in which an operating voltage is generated using an internal voltage or a second mode in which the operating voltage is generated using an external voltage, and to provide the operating voltage to the memory block, and a control logic configured to measure and store a first rising time during which the operating voltage rises to a target level in the first mode, and to control the voltage generation circuit so that a second rising time during which the operating voltage rises to the target level in the second mode is equal to or longer than the first rising time.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: The present technology includes a voltage generator and a memory device including the voltage generator. The voltage generator includes an operation code determiner configured to output a clock control code including the number of planes in response to an operation code, a clock group configured to simultaneously generate clocks having different periods according to the clock control code, and a pump group configured to perform a pumping operation according to the clocks and output operation voltages.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory block, a voltage generation circuit configured to operate in a first mode in which an operating voltage is generated using an internal voltage or a second mode in which the operating voltage is generated using an external voltage, and to provide the operating voltage to the memory block, and a control logic configured to measure and store a first rising time during which the operating voltage rises to a target level in the first mode, and to control the voltage generation circuit so that a second rising time during which the operating voltage rises to the target level in the second mode is equal to or longer than the first rising time.

Abstract: A memory device may include: a memory cell array including a plurality of planes; and a voltage generation circuit including a master pump component and at least one or more sub-pump components that respectively correspond to the planes. During an interleaved operation, the master pump component may generate a first output voltage in response to a first pump clock, and the sub-pump components may generate second output voltages in response to second pump clocks. The master pump component and the sub-pump components may respectively provide the first output voltage and the second output voltages to the corresponding planes. During a non-interleaved operation, the master pump component and the sub-pump components may generate the first output voltage in response to the first pump clock and provide the first output voltage to a selected plane of the plurality of planes.

Abstract: The present disclosure relates to method of operating a memory device, the memory device includes a memory cell array, a voltage generator, and control logic. The voltage generator configured to increase a power supply voltage. The control logic is configured to store a time based on the increased power supply voltage and a reference voltage. The reference voltage is a voltage level used to perform an operation on the memory cell array.

Abstract: Disclosed is an electronic device and a method for processing authentication. The electronic device includes a communication circuit; a display; a memory; and at least one processor electrically connected to the communication circuit, the display, and the memory, wherein the memory stores instructions that cause the at least one processor to identify whether the electronic device is mounted on a first external electronic device, execute at least one application for an authentication based at least part of the identification, detect a second external electronic device, which can transmit authentication information related to the authentication, receive at least one piece of information related to the authentication from the second external electronic device based at least partially on the detection outcome, and perform authentication based on the received authentication information.

Abstract: The present disclosure relates to method of operating a memory device, the memory device includes a memory cell array, a voltage generator, and control logic. The voltage generator configured to increase a power supply voltage. The control logic is configured to store a time based on the increased power supply voltage and a reference voltage. The reference voltage is a voltage level used to perform an operation on the memory cell array.