Patents by Inventor Hyun-Chul Hwang
Hyun-Chul Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240135744Abstract: A display device comprises a display panel comprising an image display area and a non-display area, display pixels comprising light-emitting elements in the image display area and pixel driving units connected to the light-emitting elements, light-sensing pixels comprising photo-detecting units in a fingerprint sensing area in the image display area, and sense driving units connected to the photo-detecting units, a light-sensing reset driver configured to supply reset signals to the sense driving units of the light-sensing pixels for at least each horizontal line among the light-sensing pixels in response to a line select signal from a display driving circuit; and a fingerprint scan driver configured to sequentially supply a fingerprint scan signal to the sense driving units of the light-sensing pixels in response to a fingerprint scan control signal from the display driving circuit.Type: ApplicationFiled: September 27, 2023Publication date: April 25, 2024Inventors: Hyun Dae LEE, Il Nam KIM, Hyoung Wook JANG, Kang Bin JO, Go Eun CHA, Hee Chul HWANG
-
Publication number: 20240128112Abstract: An overlay measurement device includes a transmission and receipt part and a processor connecting to the transmission and receipt part electrically. The processor obtains data transmitted from a user terminal through the transmission and receipt part, analyzes a recipe included in the data, and performs optimization of measurement options of a wafer, based on the recipe, after the recipe is analyzed.Type: ApplicationFiled: July 28, 2023Publication date: April 18, 2024Applicant: AUROS TECHNOLOGY, INC.Inventors: Sol-Lee HWANG, Hee-Chul LIM, Dong-Won JUNG, Min-Ho LEE, Hyun-Kyoo SHON
-
Patent number: 11960214Abstract: There are provided a computer-readable storage medium and an overlay measurement device therefor that records a data structure for storing data controlling an operation of an overlay measurement device. In a computer-readable storage medium that records a data structure for storing data controlling an operation of an overlay measurement device in one embodiment, the data includes information of a recipe that is input to allow the overlay measurement device to measure characteristics of a wafer through a manager program installed in a user terminal, and unique information of the overlay measurement device.Type: GrantFiled: May 3, 2023Date of Patent: April 16, 2024Assignee: AUROS TECHNOLOGY, INC.Inventors: Sol-Lee Hwang, Dong-Won Jung, Hee-Chul Lim, Hyun-Kyoo Shon, Min-Ho Lee
-
Patent number: 11924988Abstract: A display apparatus including a display and a supporter. The supporter being mounted on the display and configured to support the display and rotate the display module between a first position and a second position. The supporter including a drive motor, a first gear, and a detection sensor. The drive motor configured to supply a driving force to rotate the display. The first gear configured to rotate together with the display by receiving the driving force from the drive motor. The detection sensor configured to detect a rotation amount of a second gear configured to rotate in with the first gear.Type: GrantFiled: December 23, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Yong Choi, Young Chul Kim, Ji Su Kim, Hun Sung Kim, Sung Yong Park, Jin Soo Shin, Dae Sik Yoon, Yong Yeon Hwang
-
Publication number: 20220149821Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.Type: ApplicationFiled: July 26, 2021Publication date: May 12, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun Chul HWANG, Min Su KIM
-
Patent number: 11289138Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.Type: GrantFiled: November 25, 2020Date of Patent: March 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-shin Yoo, Min-su Kim, Hyun-chul Hwang
-
Publication number: 20210158847Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.Type: ApplicationFiled: November 25, 2020Publication date: May 27, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-shin YOO, Min-su KIM, Hyun-chul HWANG
-
Patent number: 10938383Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.Type: GrantFiled: February 27, 2018Date of Patent: March 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Chul Hwang, Jong-Kyu Ryu, Min-Su Kim
-
Patent number: 10911032Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: GrantFiled: July 29, 2019Date of Patent: February 2, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Hwang, Min-Su Kim, Dae-Seong Lee
-
Patent number: 10867645Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.Type: GrantFiled: April 4, 2019Date of Patent: December 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-shin Yoo, Min-su Kim, Hyun-chul Hwang
-
Patent number: 10651828Abstract: A flip-flop generates a first feedback signal using a signal generated inside the flip-flop. The flip-flop includes a first stage circuit, a second stage circuit and a third stage circuit. The first stage circuit receives a first data signal and a clock signal and generates a first internal signal through a first node. The second stage circuit receives the first internal signal, the clock signal, and the first feedback signal and generates a second internal signal through a second node. The third stage circuit generates a second data signal by latching the second internal signal when the clock signal is at a first level, using the second internal signal and the clock signal. The second stage circuit cuts off at least one first current path between the second node and a power supply, based on the first feedback signal, when the clock signal is at a second level.Type: GrantFiled: June 15, 2017Date of Patent: May 12, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Hwang, Ah-Reum Kim, Min-Su Kim
-
Publication number: 20190376907Abstract: A light-scattering dust sensor includes: a light scattering region; a light emitter configured to emit light to the light scattering region; a light receiver configured to receive scattered light generated in the light scattering region; and an emitted light limiter located between the light emitter and the light scattering region, wherein the light emitted by the light emitter includes: peripheral light; and central light having an intensity that is more uniform than an intensity of the peripheral light, wherein the emitted light limiter is configured to block part of the emitted light, wherein the part of the emitted light blocked by the emitted light limiter includes the peripheral light.Type: ApplicationFiled: December 12, 2018Publication date: December 12, 2019Inventors: Sang Ick Park, Do Hoon Kim, Hyun Chul Hwang, Myeong Yong Lee, Dong Ju Kim
-
Publication number: 20190379361Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: ApplicationFiled: July 29, 2019Publication date: December 12, 2019Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul HWANG, Min-Su Kim, Dae-Seong Lee
-
Publication number: 20190311751Abstract: A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.Type: ApplicationFiled: April 4, 2019Publication date: October 10, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-shin YOO, Min-su KIM, Hyun-chul HWANG
-
Patent number: 10396761Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: GrantFiled: August 4, 2017Date of Patent: August 27, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Hwang, Min-Su Kim, Dae-Seong Lee
-
Publication number: 20190074825Abstract: A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.Type: ApplicationFiled: February 27, 2018Publication date: March 7, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Chul HWANG, Jong-Kyu RYU, Min-Su KIM
-
Patent number: 10184984Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.Type: GrantFiled: April 28, 2016Date of Patent: January 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Chul Hwang, Dae-Seong Lee, Min-Su Kim
-
Patent number: 10033386Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit is configured to generate a voltage level at a first node based on a voltage level of input data, an inverted value of the voltage level at the first node, a voltage level of a clock signal, and a voltage level at a second node; and the second circuit is configured to generate the voltage level at the second node based on the voltage level of input data, an inverted value of the voltage level at the second node, the voltage level of the clock signal, and the inverted value of the voltage level at the first node. When the clock signal is at a first level, the first and second nodes have different logical levels. When the clock signal is at a second level, the first and second nodes have the same logical level.Type: GrantFiled: July 27, 2017Date of Patent: July 24, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul Hwang, Min-Su Kim
-
Publication number: 20180145661Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.Type: ApplicationFiled: August 4, 2017Publication date: May 24, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Hyun-Chul HWANG, Min-Su Kim, Dae-Seong Lee
-
Patent number: D886647Type: GrantFiled: December 11, 2018Date of Patent: June 9, 2020Assignee: SAMYOUNG S&C CO., LTD.Inventors: Sang Ick Park, Do Hoon Kim, Hyun Chul Hwang, Myeong Yong Lee