Patents by Inventor Hyun-Chul Sagong
Hyun-Chul Sagong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11488877Abstract: A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.Type: GrantFiled: November 15, 2018Date of Patent: November 1, 2022Inventors: Hyun Chul Sagong, June Kyun Park, Hyun Jin Kim, Ki Hyun Choi, Sang Woo Pae
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Patent number: 11245018Abstract: A semiconductor device may include an active region extending primarily in a first direction on a substrate. A gate structure may be disposed to intersect the active region, and extend primarily in a second direction intersecting the first direction. A gate isolation pattern may contact one end of the gate structure. The gate structure may include a plurality of portions each having different widths in the first direction, and the gate isolation pattern may have a width greater than a width of at least one of the plurality of portions of the gate structure.Type: GrantFiled: May 17, 2019Date of Patent: February 8, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Chul Sagong, Sung Eun Kim, Jin Woo Kim, June Kyun Park, Sang Woo Pae, Ki Hyun Choi
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Patent number: 10943900Abstract: A semiconductor device is provided. The Semiconductor device includes a substrate, a first fin type pattern and a second fin type pattern which protrude from an upper surface of the substrate and are spaced apart from each other, a first semiconductor pattern on the first fin type pattern, a second semiconductor pattern on the second tin type pattern and a blocking pattern between the first semiconductor pattern and the second semiconductor pattern, a part of the first semiconductor pattern being inserted in the blocking pattern.Type: GrantFiled: April 26, 2019Date of Patent: March 9, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun Chul Sagong, Sang Woo Pae, Ki Hyun Choi, June Kyun Park, Uk Jin Jung
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Publication number: 20200185383Abstract: A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.Type: ApplicationFiled: May 21, 2019Publication date: June 11, 2020Inventors: Jin Woo KIM, Choelhwyi BAE, Yang Gyeom KIM, Sung Eun KIM, Sang Woo PAE, Hyun Chul SAGONG
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Publication number: 20200144384Abstract: A semiconductor device may include an active region extending primarily in a first direction on a substrate. A gate structure may be disposed to intersect the active region, and extend primarily in a second direction intersecting the first direction. A gate isolation pattern may contact one end of the gate structure. The gate structure may include a plurality of portions each having different widths in the first direction, and the gate isolation pattern may have a width greater than a width of at least one of the plurality of portions of the gate structure.Type: ApplicationFiled: May 17, 2019Publication date: May 7, 2020Inventors: HYUN CHUL SAGONG, SUNG EUN KIM, JIN WOO KIM, JUNE KYUN PARK, SANG WOO PAE, KI HYUN CHOI
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Publication number: 20200035675Abstract: A semiconductor device is provided. The Semiconductor device includes a substrate, a first fin type pattern and a second fin type pattern which protrude from an upper surface of the substrate and are spaced apart from each other, a first semiconductor pattern on the first fin type pattern, a second semiconductor pattern on the second tin type pattern and a blocking pattern between the first semiconductor pattern and the second semiconductor pattern, a part of the first semiconductor pattern being inserted in the blocking pattern.Type: ApplicationFiled: April 26, 2019Publication date: January 30, 2020Inventors: HYUN CHUL SAGONG, Sang Woo PAE, Ki Hyun CHOI, June Kyun PARK, Uk Jin JUNG
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Patent number: 10490477Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.Type: GrantFiled: May 30, 2016Date of Patent: November 26, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Chul Sagong, Sang-Woo Pae, Seung-Jin Choo
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Publication number: 20190326187Abstract: A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.Type: ApplicationFiled: November 15, 2018Publication date: October 24, 2019Inventors: Hyun Chul SAGONG, June Kyun PARK, Hyun Jin KIM, Ki Hyun CHOI, Sang Woo PAE
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Patent number: 10262998Abstract: A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure.Type: GrantFiled: November 8, 2016Date of Patent: April 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-chul Sagong, Sang-woo Pae, Sung-young Yoon
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Patent number: 9892977Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.Type: GrantFiled: September 20, 2016Date of Patent: February 13, 2018Assignee: Samsing Electronics Co., Ltd.Inventors: Sang Woo Pae, Hyun Chul Sagong, Jin Ju Kim, June Kyun Park
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Patent number: 9728486Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.Type: GrantFiled: December 7, 2015Date of Patent: August 8, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Woo Pae, Jong-Wook Jeon, Seung-Jin Choo, Hyun-Chul Sagong, Jae-Hee Choi
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Publication number: 20170141113Abstract: A semiconductor device includes a substrate including a first active area extending in a first direction and a second active area extending in a second direction and connected to the first active area; first and second gate structures respectively crossing the first and second active areas; a first region in an area where the first and second active areas are connected to each other, the first region being on a first side of each of the first and second gate structures; a second region in the first active area on the other side of the first gate structure; and a third region formed in the second active area on the other side of the second gate structure.Type: ApplicationFiled: November 8, 2016Publication date: May 18, 2017Inventors: Hyun-chul Sagong, Sang-woo Pae, Sung-young Yoon
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Publication number: 20170140997Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.Type: ApplicationFiled: September 20, 2016Publication date: May 18, 2017Inventors: Sang Woo Pae, Hyun Chul Sagong, Jin Ju Kim, June Kyun Park
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Publication number: 20170069615Abstract: There is provided a semiconductor device capable of suppressing generation of leakage current of a diode, by applying a voltage to a gate of a gated junction diode (GJD). The semiconductor device includes an internal circuit connected with an input-output terminal, and an electrostatic discharge (ESD) protection circuit configured to protect the internal circuit from ESD, the ESD protection circuit including a first diode, wherein the first diode includes a first gate which is formed on a substrate and to which a first recovery voltage is applied, a first well of a first conductivity type which is formed within the substrate and under the first gate, a first impurity region of the first conductivity type which is formed on one side of the first gate and within the first well and is higher in doping concentration than that of the first well, and a second impurity region of a second conductivity type which is formed on other side of the first gate and within the first well.Type: ApplicationFiled: August 17, 2016Publication date: March 9, 2017Inventors: HYUN-CHUL SAGONG, SANG-WOO PAE, SEUNG-JIN CHOO, WOO-KYUM LEE
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Publication number: 20170018479Abstract: A semiconductor device includes a substrate, a thermal conduction layer on the substrate, a first wire pattern on the thermal conduction layer, a first semiconductor pattern a second semiconductor pattern, and a gate electrode between the first semiconductor pattern and the second semiconductor pattern. The gate electrode surrounds a periphery of the first wire pattern. A concentration of impurity of the thermal conduction layer is different from that of the substrate. The first wire pattern includes a first end and a second end. The concentration of impurity contained in the first wire pattern is higher than that contained in the thermal conduction layer and that contained in the substrate. The first semiconductor pattern is in contact with the first end of the first wire pattern and the thermal conduction layer. The second semiconductor pattern is in contact with the second end of the first wire pattern.Type: ApplicationFiled: May 30, 2016Publication date: January 19, 2017Inventors: Hyun-Chul SAGONG, Sang-Woo PAE, Seung-Jin CHOO
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Publication number: 20160233144Abstract: A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.Type: ApplicationFiled: December 7, 2015Publication date: August 11, 2016Inventors: Sang-Woo Pae, Jong-Wook Jeon, Seung-Jin Choo, Hyun-Chul Sagong, Jae-Hee Choi